g32r4xx_ddl_adc12.h File Reference

Header file of ADC DDL module. More...

#include "g32r4xx.h"

Go to the source code of this file.

Data Structures
struct	DDL_ADC12_InitTypeDef
	Structure definition of some features of ADC instance. More...
struct	DDL_ADC12_REG_InitTypeDef
	Structure definition of some features of ADC group regular. More...
struct	DDL_ADC12_INJ_InitTypeDef
	Structure definition of some features of ADC group injected. More...

Macros
#define	ADC12_SQR1_REGOFFSET   (0x00000000UL)
#define	ADC12_SQR2_REGOFFSET   (0x00000100UL)
#define	ADC12_SQR3_REGOFFSET   (0x00000200UL)
#define	ADC12_REG_SQRX_REGOFFSET_MASK   (ADC12_SQR1_REGOFFSET | ADC12_SQR2_REGOFFSET | ADC12_SQR3_REGOFFSET)
#define	ADC12_SQRX_REGOFFSET_POS   (8UL) /* Position of bits ADC12_SQRx_REGOFFSET in ADC12_REG_SQRX_REGOFFSET_MASK */
#define	ADC12_REG_RANK_ID_SQRX_MASK   (0x1F)
#define	ADC12_REG_RANK_1_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ1_Pos)
#define	ADC12_REG_RANK_2_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ2_Pos)
#define	ADC12_REG_RANK_3_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ3_Pos)
#define	ADC12_REG_RANK_4_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ4_Pos)
#define	ADC12_REG_RANK_5_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ5_Pos)
#define	ADC12_REG_RANK_6_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ6_Pos)
#define	ADC12_REG_RANK_7_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ7_Pos)
#define	ADC12_REG_RANK_8_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ8_Pos)
#define	ADC12_REG_RANK_9_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ9_Pos)
#define	ADC12_REG_RANK_10_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ10_Pos)
#define	ADC12_REG_RANK_11_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ11_Pos)
#define	ADC12_REG_RANK_12_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ12_Pos)
#define	ADC12_REG_RANK_13_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ13_Pos)
#define	ADC12_REG_RANK_14_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ14_Pos)
#define	ADC12_REG_RANK_15_SQRX_BITOFFSET_POS   (ADC_SQR3_SQ15_Pos)
#define	ADC12_REG_RANK_16_SQRX_BITOFFSET_POS   (ADC_SQR3_SQ16_Pos)
#define	ADC12_JDR1_REGOFFSET   (0x00000000UL)
#define	ADC12_JDR2_REGOFFSET   (0x00000100UL)
#define	ADC12_JDR3_REGOFFSET   (0x00000200UL)
#define	ADC12_JDR4_REGOFFSET   (0x00000300UL)
#define	ADC12_INJ_JDRX_REGOFFSET_MASK
#define	ADC12_INJ_RANK_ID_JSQR_MASK   (0x1F)
#define	ADC12_JDRX_REGOFFSET_POS   (8UL) /* Position of bits ADC12_JDRx_REGOFFSET in ADC12_INJ_JDRX_REGOFFSET_MASK */
#define	ADC12_INJ_RANK_1_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ1_Pos)
#define	ADC12_INJ_RANK_3_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ3_Pos)
#define	ADC12_INJ_RANK_2_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ2_Pos)
#define	ADC12_INJ_RANK_4_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ4_Pos)
#define	ADC12_REG_TRIG_EXT_EDGE_DEFAULT   (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */
#define	ADC12_REG_TRIG_SOURCE_MASK
#define	ADC12_REG_TRIG_EDGE_MASK
#define	ADC12_REG_TRIG_EXTSEL_BITOFFSET_POS   (ADC_CFGR_EXTSEL_Pos)
#define	ADC12_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
#define	ADC12_INJ_TRIG_EXT_EDGE_DEFAULT   (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */
#define	ADC12_INJ_TRIG_SOURCE_MASK
#define	ADC12_INJ_TRIG_EDGE_MASK
#define	ADC12_INJ_TRIG_EXTSEL_BITOFFSET_POS   (ADC_JSQR_JEXTSEL_Pos)
#define	ADC12_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
#define	ADC12_CHANNEL_ID_NUMBER_MASK   (ADC_CFGR_AWD1CH)
#define	ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS   (ADC_CFGR_AWD1CH_Pos)
#define	ADC12_CHANNEL_ID_MASK
#define	ADC12_CHANNEL_ID_NUMBER_MASK_POSBIT0   (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC12_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC12_CHANNEL_NUMBER_MASK" in register]) */
#define	ADC12_CHANNEL_ID_INTERNAL_CH   (0x80000000UL) /* Marker of internal channel */
#define	ADC12_CHANNEL_ID_INTERNAL_CH_2   (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define	ADC12_CHANNEL_ID_INTERNAL_CH_MASK   (ADC12_CHANNEL_ID_INTERNAL_CH | ADC12_CHANNEL_ID_INTERNAL_CH_2)
#define	ADC12_SMPR1_REGOFFSET   (0x00000000UL)
#define	ADC12_SMPR2_REGOFFSET   (0x02000000UL)
#define	ADC12_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC12_SMPR1_REGOFFSET | ADC12_SMPR2_REGOFFSET)
#define	ADC12_SMPRX_REGOFFSET_POS   (25UL) /* Position of bits ADC12_SMPRx_REGOFFSET in ADC12_CHANNEL_SMPRX_REGOFFSET_MASK */
#define	ADC12_CHANNEL_SMPx_BITOFFSET_MASK   (0x01F00000UL)
#define	ADC12_CHANNEL_SMPx_BITOFFSET_POS   (20UL) /* Value equivalent to bitfield "ADC12_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define	ADC12_CHANNEL_0_NUMBER   (0x00000000UL)
#define	ADC12_CHANNEL_1_NUMBER   (ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_2_NUMBER   (ADC_CFGR_AWD1CH_1)
#define	ADC12_CHANNEL_3_NUMBER   (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_4_NUMBER   (ADC_CFGR_AWD1CH_2)
#define	ADC12_CHANNEL_5_NUMBER   (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_6_NUMBER   (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define	ADC12_CHANNEL_7_NUMBER   (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_8_NUMBER   (ADC_CFGR_AWD1CH_3)
#define	ADC12_CHANNEL_9_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_10_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
#define	ADC12_CHANNEL_11_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_12_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
#define	ADC12_CHANNEL_13_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_14_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define	ADC12_CHANNEL_15_NUMBER   (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define	ADC12_CHANNEL_0_SMP   (ADC12_SMPR1_REGOFFSET | (( 0UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define	ADC12_CHANNEL_1_SMP   (ADC12_SMPR1_REGOFFSET | (( 4UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define	ADC12_CHANNEL_2_SMP   (ADC12_SMPR1_REGOFFSET | (( 8UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define	ADC12_CHANNEL_3_SMP   (ADC12_SMPR1_REGOFFSET | ((12UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define	ADC12_CHANNEL_4_SMP   (ADC12_SMPR1_REGOFFSET | ((16UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define	ADC12_CHANNEL_5_SMP   (ADC12_SMPR1_REGOFFSET | ((20UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define	ADC12_CHANNEL_6_SMP   (ADC12_SMPR1_REGOFFSET | ((24UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define	ADC12_CHANNEL_7_SMP   (ADC12_SMPR1_REGOFFSET | ((28UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define	ADC12_CHANNEL_8_SMP   (ADC12_SMPR2_REGOFFSET | (( 0UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP8" position in register */
#define	ADC12_CHANNEL_9_SMP   (ADC12_SMPR2_REGOFFSET | (( 4UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP9" position in register */
#define	ADC12_CHANNEL_10_SMP   (ADC12_SMPR2_REGOFFSET | (( 8UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define	ADC12_CHANNEL_11_SMP   (ADC12_SMPR2_REGOFFSET | ((12UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define	ADC12_CHANNEL_12_SMP   (ADC12_SMPR2_REGOFFSET | ((16UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define	ADC12_CHANNEL_13_SMP   (ADC12_SMPR2_REGOFFSET | ((20UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define	ADC12_CHANNEL_14_SMP   (ADC12_SMPR2_REGOFFSET | ((24UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define	ADC12_CHANNEL_15_SMP   (ADC12_SMPR2_REGOFFSET | ((28UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define	ADC12_AWD_CR1_REGOFFSET   (0x00000000UL)
#define	ADC12_AWD_CR2_REGOFFSET   (0x00100000UL)
#define	ADC12_AWD_CR3_REGOFFSET   (0x00200000UL)
#define	ADC12_AWD_CR12_REGOFFSETGAP_MASK   (ADC_AWD2CR_AWD2CH_0)
#define	ADC12_AWD_CR12_REGOFFSETGAP_VAL   (0x00000010UL)
#define	ADC12_AWD_CRX_REGOFFSET_MASK   (ADC12_AWD_CR1_REGOFFSET | ADC12_AWD_CR2_REGOFFSET | ADC12_AWD_CR3_REGOFFSET)
#define	ADC12_AWD_CR1_CHANNEL_MASK   (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	ADC12_AWD_CR23_CHANNEL_MASK   (ADC_AWD2CR_AWD2CH)
#define	ADC12_AWD_CR_ALL_CHANNEL_MASK   (ADC12_AWD_CR1_CHANNEL_MASK | ADC12_AWD_CR23_CHANNEL_MASK)
#define	ADC12_AWD_CRX_REGOFFSET_POS   (20UL) /* Position of bits ADC12_AWD_CRx_REGOFFSET in ADC12_AWD_CRX_REGOFFSET_MASK */
#define	ADC12_AWD_TR1_REGOFFSET   (ADC12_AWD_CR1_REGOFFSET)
#define	ADC12_AWD_TR2_REGOFFSET   (ADC12_AWD_CR2_REGOFFSET)
#define	ADC12_AWD_TR3_REGOFFSET   (ADC12_AWD_CR3_REGOFFSET)
#define	ADC12_AWD_TRX_REGOFFSET_MASK   (ADC12_AWD_TR1_REGOFFSET | ADC12_AWD_TR2_REGOFFSET | ADC12_AWD_TR3_REGOFFSET)
#define	ADC12_AWD_TRX_REGOFFSET_POS   (ADC12_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC12_SQRx_REGOFFSET in ADC12_AWD_TRX_REGOFFSET_MASK */
#define	ADC12_AWD_TRX_BIT_HIGH_MASK   (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define	ADC12_AWD_TRX_BIT_HIGH_POS   (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define	ADC12_AWD_TRX_BIT_HIGH_SHIFT4   (ADC12_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC12_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define	ADC12_OFR0_REGOFFSET   (0x00000000UL)
#define	ADC12_OFR1_REGOFFSET   (0x00000001UL)
#define	ADC12_OFR2_REGOFFSET   (0x00000002UL)
#define	ADC12_OFR3_REGOFFSET   (0x00000003UL)
#define	ADC12_OFRx_REGOFFSET_MASK
#define	ADC12_CFGR_AWD1SGL_BITOFFSET_POS   (ADC_CFGR_AWD1SGL_Pos)
#define	ADC12_CFGR_AWD1EN_BITOFFSET_POS   (ADC_CFGR_AWD1EN_Pos)
#define	ADC12_CFGR_JAWD1EN_BITOFFSET_POS   (ADC_CFGR_JAWD1EN_Pos)
#define	ADC12_TR1_HT1_BITOFFSET_POS   (ADC_TR1_HT1_Pos)
#define	ADC12_CR_BITS_PROPERTY_RS   (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define	DDL_ADC12_REG_TRIG_SOFTWARE   (0x00000000UL)
#define	DDL_ADC12_REG_TRIG_EXT_TMR1_CC1   (ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_TMR1_CC2   (ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_TMR1_CC3   (ADC_CFGR_EXTSEL_1 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_TMR2_CC2   (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_TMR3_TRGO   (ADC_CFGR_EXTSEL_2 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_TMR4_CC4   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_EINT_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_REG_TRIG_EXT_RISING   (ADC_CFGR_EXTEN_0)
#define	DDL_ADC12_REG_TRIG_EXT_DISABLE   (0x00000000UL)
#define	DDL_ADC12_REG_SEQ_SCAN_DISABLE   (0x00000000UL)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_2RANKS   ( ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_3RANKS   ( ADC_SQR1_RL_1 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_4RANKS   ( ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_5RANKS   ( ADC_SQR1_RL_2 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_6RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_7RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_8RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_9RANKS   (ADC_SQR1_RL_3 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_10RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_11RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_12RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_13RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_2 )
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_14RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_2 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_15RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_2 | ADC_SQR1_RL_1)
#define	DDL_ADC12_REG_SEQ_SCAN_ENABLE_16RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define	DDL_ADC12_REG_SEQ_DISCONT_DISABLE   (0x00000000UL)
#define	DDL_ADC12_REG_SEQ_DISCONT_1RANK   ( ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_2RANKS   ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_3RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_4RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_7RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_SEQ_DISCONT_8RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC12_REG_RANK_1   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_1_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_2   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_2_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_3   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_3_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_4   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_4_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_5   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_5_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_6   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_6_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_7   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_7_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_8   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_8_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_9   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_9_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_10   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_10_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_11   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_11_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_12   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_12_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_13   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_13_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_14   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_14_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_15   (ADC12_SQR3_REGOFFSET | ADC12_REG_RANK_15_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_REG_RANK_16   (ADC12_SQR3_REGOFFSET | ADC12_REG_RANK_16_SQRX_BITOFFSET_POS)
#define	DDL_ADC12_INJ_SEQ_SCAN_DISABLE   (0x00000000UL)
#define	DDL_ADC12_INJ_SEQ_SCAN_ENABLE_2RANKS   ( ADC_JSQR_JL_0)
#define	DDL_ADC12_INJ_SEQ_SCAN_ENABLE_3RANKS   (ADC_JSQR_JL_1 )
#define	DDL_ADC12_INJ_SEQ_SCAN_ENABLE_4RANKS   (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define	DDL_ADC12_INJ_SEQ_DISCONT_DISABLE   (0x00000000UL)
#define	DDL_ADC12_INJ_SEQ_DISCONT_1RANK   (ADC_CFGR_JDISCEN)
#define	DDL_ADC12_DMA_REG_REGULAR_DATA   (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by DDL function @ref DDL_ADC12_REG_ReadConversionData32() and other functions @ref DDL_ADC12_REG_ReadConversionDatax() */
#define	DDL_ADC12_JOFFSET_1   ADC12_OFR0_REGOFFSET
#define	DDL_ADC12_JOFFSET_2   ADC12_OFR1_REGOFFSET
#define	DDL_ADC12_JOFFSET_3   ADC12_OFR2_REGOFFSET
#define	DDL_ADC12_JOFFSET_4   ADC12_OFR3_REGOFFSET
#define	DDL_ADC12_CHANNEL_0   (ADC12_CHANNEL_0_NUMBER | ADC12_CHANNEL_0_SMP)
#define	DDL_ADC12_CHANNEL_1   (ADC12_CHANNEL_1_NUMBER | ADC12_CHANNEL_1_SMP)
#define	DDL_ADC12_CHANNEL_2   (ADC12_CHANNEL_2_NUMBER | ADC12_CHANNEL_2_SMP)
#define	DDL_ADC12_CHANNEL_3   (ADC12_CHANNEL_3_NUMBER | ADC12_CHANNEL_3_SMP)
#define	DDL_ADC12_CHANNEL_4   (ADC12_CHANNEL_4_NUMBER | ADC12_CHANNEL_4_SMP)
#define	DDL_ADC12_CHANNEL_5   (ADC12_CHANNEL_5_NUMBER | ADC12_CHANNEL_5_SMP)
#define	DDL_ADC12_CHANNEL_6   (ADC12_CHANNEL_6_NUMBER | ADC12_CHANNEL_6_SMP)
#define	DDL_ADC12_CHANNEL_7   (ADC12_CHANNEL_7_NUMBER | ADC12_CHANNEL_7_SMP)
#define	DDL_ADC12_CHANNEL_8   (ADC12_CHANNEL_8_NUMBER | ADC12_CHANNEL_8_SMP)
#define	DDL_ADC12_CHANNEL_9   (ADC12_CHANNEL_9_NUMBER | ADC12_CHANNEL_9_SMP)
#define	DDL_ADC12_CHANNEL_10   (ADC12_CHANNEL_10_NUMBER | ADC12_CHANNEL_10_SMP)
#define	DDL_ADC12_CHANNEL_11   (ADC12_CHANNEL_11_NUMBER | ADC12_CHANNEL_11_SMP)
#define	DDL_ADC12_CHANNEL_12   (ADC12_CHANNEL_12_NUMBER | ADC12_CHANNEL_12_SMP)
#define	DDL_ADC12_CHANNEL_13   (ADC12_CHANNEL_13_NUMBER | ADC12_CHANNEL_13_SMP)
#define	DDL_ADC12_CHANNEL_14   (ADC12_CHANNEL_14_NUMBER | ADC12_CHANNEL_14_SMP)
#define	DDL_ADC12_CHANNEL_15   (ADC12_CHANNEL_15_NUMBER | ADC12_CHANNEL_15_SMP)
#define	DDL_ADC12_REG_CONV_SINGLE   (0x00000000UL)
#define	DDL_ADC12_REG_CONV_CONTINUOUS   (ADC_CFGR_CONT)
#define	DDL_ADC12_REG_DMA_TRANSFER_DISABLE   (0x00000000UL)
#define	DDL_ADC12_REG_DMA_TRANSFER_ENABLE   ( ADC_CFGR_DMAEN)
#define	DDL_ADC12_INJ_TRIG_SOFTWARE   (0x00000000UL)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR1_TRGO   (ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR1_CC4   (ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR2_TRGO   (ADC_JSQR_JEXTSEL_1 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR2_CC1   (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR3_CC4   (ADC_JSQR_JEXTSEL_2 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_TMR4_TRGO   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_EINT_LINE15   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	DDL_ADC12_INJ_TRIG_EXT_RISING   ( ADC_JSQR_JEXTEN_0)
#define	DDL_ADC12_INJ_TRIG_EXT_DISABLE   (0x00000000UL)
#define	DDL_ADC12_INJ_RANK_1   (ADC12_JDR1_REGOFFSET | ADC12_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define	DDL_ADC12_INJ_RANK_2   (ADC12_JDR2_REGOFFSET | ADC12_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define	DDL_ADC12_INJ_RANK_3   (ADC12_JDR3_REGOFFSET | ADC12_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define	DDL_ADC12_INJ_RANK_4   (ADC12_JDR4_REGOFFSET | ADC12_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define	DDL_ADC12_INJ_TRIG_INDEPENDENT   (0x00000000UL)
#define	DDL_ADC12_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)
#define	DDL_ADC12_SAMPLINGTIME_7CYCLES   (0x00000000)
#define	DDL_ADC12_SAMPLINGTIME_16CYCLES   (ADC_SMPR1_SMP0_0)
#define	DDL_ADC12_SAMPLINGTIME_27CYCLES   (ADC_SMPR1_SMP0_1)
#define	DDL_ADC12_SAMPLINGTIME_32CYCLES   (ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define	DDL_ADC12_SAMPLINGTIME_67CYCLES   (ADC_SMPR1_SMP0_2)
#define	DDL_ADC12_SAMPLINGTIME_96CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define	DDL_ADC12_SAMPLINGTIME_128CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define	DDL_ADC12_SAMPLINGTIME_256CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define	DDL_ADC12_AWD1   (ADC12_AWD_CR1_CHANNEL_MASK | ADC12_AWD_CR1_REGOFFSET)
#define	DDL_ADC12_AWD_DISABLE   (0x00000000UL)
#define	DDL_ADC12_AWD_ALL_CHANNELS_REG   (ADC_CFGR_AWD1EN )
#define	DDL_ADC12_AWD_ALL_CHANNELS_INJ   (ADC_CFGR_JAWD1EN )
#define	DDL_ADC12_AWD_ALL_CHANNELS_REG_INJ   (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define	DDL_ADC12_AWD_CHANNEL_0_REG   ((DDL_ADC12_CHANNEL_0 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_0_INJ   ((DDL_ADC12_CHANNEL_0 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_0_REG_INJ   ((DDL_ADC12_CHANNEL_0 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_1_REG   ((DDL_ADC12_CHANNEL_1 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_1_INJ   ((DDL_ADC12_CHANNEL_1 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_1_REG_INJ   ((DDL_ADC12_CHANNEL_1 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_2_REG   ((DDL_ADC12_CHANNEL_2 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_2_INJ   ((DDL_ADC12_CHANNEL_2 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_2_REG_INJ   ((DDL_ADC12_CHANNEL_2 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_3_REG   ((DDL_ADC12_CHANNEL_3 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_3_INJ   ((DDL_ADC12_CHANNEL_3 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_3_REG_INJ   ((DDL_ADC12_CHANNEL_3 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_4_REG   ((DDL_ADC12_CHANNEL_4 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_4_INJ   ((DDL_ADC12_CHANNEL_4 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_4_REG_INJ   ((DDL_ADC12_CHANNEL_4 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_5_REG   ((DDL_ADC12_CHANNEL_5 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_5_INJ   ((DDL_ADC12_CHANNEL_5 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_5_REG_INJ   ((DDL_ADC12_CHANNEL_5 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_6_REG   ((DDL_ADC12_CHANNEL_6 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_6_INJ   ((DDL_ADC12_CHANNEL_6 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_6_REG_INJ   ((DDL_ADC12_CHANNEL_6 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_7_REG   ((DDL_ADC12_CHANNEL_7 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_7_INJ   ((DDL_ADC12_CHANNEL_7 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_7_REG_INJ   ((DDL_ADC12_CHANNEL_7 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_8_REG   ((DDL_ADC12_CHANNEL_8 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_8_INJ   ((DDL_ADC12_CHANNEL_8 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_8_REG_INJ   ((DDL_ADC12_CHANNEL_8 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_9_REG   ((DDL_ADC12_CHANNEL_9 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_9_INJ   ((DDL_ADC12_CHANNEL_9 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_9_REG_INJ   ((DDL_ADC12_CHANNEL_9 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_10_REG   ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_10_INJ   ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_10_REG_INJ   ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_11_REG   ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_11_INJ   ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_11_REG_INJ   ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_12_REG   ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_12_INJ   ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_12_REG_INJ   ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_13_REG   ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_13_INJ   ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_CHANNEL_13_REG_INJ   ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define	DDL_ADC12_AWD_THRESHOLD_HIGH   (ADC_TR1_HT1 )
#define	DDL_ADC12_AWD_THRESHOLD_LOW   ( ADC_TR1_LT1)
#define	DDL_ADC12_AWD_THRESHOLDS_HIGH_LOW   (ADC_TR1_HT1 | ADC_TR1_LT1)
#define	DDL_ADC12_FLAG_EOC   ADC_ISR_EOC
#define	DDL_ADC12_FLAG_EOS   ADC_ISR_EOS
#define	DDL_ADC12_FLAG_JEOC   ADC_ISR_JEOC
#define	DDL_ADC12_FLAG_JEOS   ADC_ISR_JEOS
#define	DDL_ADC12_FLAG_AWD1   ADC_ISR_AWD1
#define	DDL_ADC12_IT_EOC   ADC_IER_EOCIE
#define	DDL_ADC12_IT_EOS   ADC_IER_EOSIE
#define	DDL_ADC12_IT_JEOC   ADC_IER_JEOCIE
#define	DDL_ADC12_IT_JEOS   ADC_IER_JEOSIE
#define	DDL_ADC12_IT_AWD1   ADC_IER_AWD1IE
#define	DDL_ADC12_ALIGNMENT_LEFT   ADC_CFGR_ALIGN
#define	DDL_ADC12_ALIGNMENT_RIGHT   (0x00000000UL)
#define	__ADC12_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)
	Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define	__DDL_ADC12_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
	Helper macro to get ADC channel number in decimal format from literals DDL_ADC12_CHANNEL_x.

Functions
__STATIC_INLINE uint32_t	DDL_ADC12_DMA_GetRegAddr (ADC12_TypeDef *ADCx, uint32_t Register)
	Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void	DDL_ADC12_INJ_SetOffset (ADC12_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
	Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetOffset (ADC12_TypeDef *ADCx, uint32_t Offsety)
	Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void	DDL_ADC12_REG_SetTriggerSource (ADC12_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetTriggerSource (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t	DDL_ADC12_REG_IsTriggerSourceSWStart (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void	DDL_ADC12_REG_SetTriggerEdge (ADC12_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetTriggerEdge (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void	DDL_ADC12_REG_SetSequencerLength (ADC12_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetSequencerLength (ADC12_TypeDef *ADCx)
	Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void	DDL_ADC12_REG_SetSequencerDiscont (ADC12_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetSequencerDiscont (ADC12_TypeDef *ADCx)
	Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	DDL_ADC12_REG_SetSequencerRanks (ADC12_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetSequencerRanks (ADC12_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular sequence: channel on the selected scan sequence rank. Refer to description of function DDL_ADC12_REG_SetSequencerLength().
__STATIC_INLINE void	DDL_ADC12_REG_SetContinuousMode (ADC12_TypeDef *ADCx, uint32_t Continuous)
	Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetContinuousMode (ADC12_TypeDef *ADCx)
	Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void	DDL_ADC12_REG_SetDMATransfer (ADC12_TypeDef *ADCx, uint32_t DMATransfer)
	Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_GetDMATransfer (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void	DDL_ADC12_INJ_SetTriggerSource (ADC12_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetTriggerSource (ADC12_TypeDef *ADCx)
	Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_IsTriggerSourceSWStart (ADC12_TypeDef *ADCx)
	Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void	DDL_ADC12_INJ_SetTriggerEdge (ADC12_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Set ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetTriggerEdge (ADC12_TypeDef *ADCx)
	Get ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger.
__STATIC_INLINE void	DDL_ADC12_INJ_SetSequencerLength (ADC12_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetSequencerLength (ADC12_TypeDef *ADCx)
	Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void	DDL_ADC12_INJ_SetSequencerDiscont (ADC12_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetSequencerDiscont (ADC12_TypeDef *ADCx)
	Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	DDL_ADC12_INJ_SetSequencerRanks (ADC12_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetSequencerRanks (ADC12_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void	DDL_ADC12_INJ_SetTrigAuto (ADC12_TypeDef *ADCx, uint32_t TrigAuto)
	Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_GetTrigAuto (ADC12_TypeDef *ADCx)
	Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void	DDL_ADC12_INJ_ConfigQueueContext (ADC12_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
	Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void	DDL_ADC12_SetChannelSamplingTime (ADC12_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
	Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t	DDL_ADC12_GetChannelSamplingTime (ADC12_TypeDef *ADCx, uint32_t Channel)
	Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void	DDL_ADC12_SetAnalogWDMonitChannels (ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
	Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t	DDL_ADC12_GetAnalogWDMonitChannels (ADC12_TypeDef *ADCx, uint32_t AWDy)
	Get ADC analog watchdog monitored channel.
__STATIC_INLINE void	DDL_ADC12_ConfigAnalogWDThresholds (ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
	Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void	DDL_ADC12_SetAnalogWDThresholds (ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
	Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t	DDL_ADC12_GetAnalogWDThresholds (ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
	Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void	DDL_ADC12_Enable (ADC12_TypeDef *ADCx)
	Enable the selected ADC instance.
__STATIC_INLINE void	DDL_ADC12_Disable (ADC12_TypeDef *ADCx)
	Disable the selected ADC instance.
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabled (ADC12_TypeDef *ADCx)
	Get the selected ADC instance enable state.
__STATIC_INLINE void	DDL_ADC12_SetDataAlignment (ADC12_TypeDef *ADCx, uint32_t Alignment)
	Set ADC data alignment.
__STATIC_INLINE uint32_t	DDL_ADC12_GetDataAlignment (ADC12_TypeDef *ADCx)
	Get ADC data alignment.
__STATIC_INLINE void	DDL_ADC12_REG_StartConversion (ADC12_TypeDef *ADCx)
	Start ADC group regular conversion.
__STATIC_INLINE void	DDL_ADC12_REG_StopConversion (ADC12_TypeDef *ADCx)
	Stop ADC group regular conversion.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_IsConversionOngoing (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion state.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_IsStopConversionOngoing (ADC12_TypeDef *ADCx)
	Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t	DDL_ADC12_REG_ReadConversionData32 (ADC12_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE void	DDL_ADC12_INJ_StartConversion (ADC12_TypeDef *ADCx)
	Start ADC group injected conversion.
__STATIC_INLINE void	DDL_ADC12_INJ_StopConversion (ADC12_TypeDef *ADCx)
	Stop ADC group injected conversion.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_IsConversionOngoing (ADC12_TypeDef *ADCx)
	Get ADC group injected conversion state.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_IsStopConversionOngoing (ADC12_TypeDef *ADCx)
	Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t	DDL_ADC12_INJ_ReadConversionData32 (ADC12_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint32_t	DDL_ADC12_IsActiveFlag_EOC (ADC12_TypeDef *ADCx)
	Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t	DDL_ADC12_IsActiveFlag_EOS (ADC12_TypeDef *ADCx)
	Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t	DDL_ADC12_IsActiveFlag_JEOC (ADC12_TypeDef *ADCx)
	Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t	DDL_ADC12_IsActiveFlag_JEOS (ADC12_TypeDef *ADCx)
	Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t	DDL_ADC12_IsActiveFlag_AWD1 (ADC12_TypeDef *ADCx)
	Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void	DDL_ADC12_ClearFlag_EOC (ADC12_TypeDef *ADCx)
	Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_ClearFlag_EOS (ADC12_TypeDef *ADCx)
	Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_ClearFlag_JEOC (ADC12_TypeDef *ADCx)
	Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_ClearFlag_JEOS (ADC12_TypeDef *ADCx)
	Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_ClearFlag_AWD1 (ADC12_TypeDef *ADCx)
	Clear flag ADC analog watchdog 1.
__STATIC_INLINE void	DDL_ADC12_EnableIT_EOC (ADC12_TypeDef *ADCx)
	Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_EnableIT_EOS (ADC12_TypeDef *ADCx)
	Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_EnableIT_JEOC (ADC12_TypeDef *ADCx)
	Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_EnableIT_JEOS (ADC12_TypeDef *ADCx)
	Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_EnableIT_AWD1 (ADC12_TypeDef *ADCx)
	Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void	DDL_ADC12_DisableIT_EOC (ADC12_TypeDef *ADCx)
	Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_DisableIT_EOS (ADC12_TypeDef *ADCx)
	Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_DisableIT_JEOC (ADC12_TypeDef *ADCx)
	Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	DDL_ADC12_DisableIT_JEOS (ADC12_TypeDef *ADCx)
	Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	DDL_ADC12_DisableIT_AWD1 (ADC12_TypeDef *ADCx)
	Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabledIT_EOC (ADC12_TypeDef *ADCx)
	Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabledIT_EOS (ADC12_TypeDef *ADCx)
	Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabledIT_JEOC (ADC12_TypeDef *ADCx)
	Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabledIT_JEOS (ADC12_TypeDef *ADCx)
	Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	DDL_ADC12_IsEnabledIT_AWD1 (ADC12_TypeDef *ADCx)
	Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus	DDL_ADC12_DeInit (ADC12_TypeDef *ADCx)
	De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus	DDL_ADC12_Init (ADC12_TypeDef *ADCx, DDL_ADC12_InitTypeDef *ADC_InitStruct)
	Initialize some features of ADC instance.
void	DDL_ADC12_StructInit (DDL_ADC12_InitTypeDef *ADC_InitStruct)
	Set each DDL_ADC12_InitTypeDef field to default value.
ErrorStatus	DDL_ADC12_REG_Init (ADC12_TypeDef *ADCx, DDL_ADC12_REG_InitTypeDef *ADC_REG_InitStruct)
	Initialize some features of ADC group regular.
void	DDL_ADC12_REG_StructInit (DDL_ADC12_REG_InitTypeDef *ADC_REG_InitStruct)
	Set each DDL_ADC12_REG_InitTypeDef field to default value.
ErrorStatus	DDL_ADC12_INJ_Init (ADC12_TypeDef *ADCx, DDL_ADC12_INJ_InitTypeDef *ADC_INJ_InitStruct)
	Initialize some features of ADC group injected.
void	DDL_ADC12_INJ_StructInit (DDL_ADC12_INJ_InitTypeDef *ADC_INJ_InitStruct)
	Set each DDL_ADC12_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC DDL module.

Attention

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The original code has been modified by Geehy Semiconductor.

Copyright (c) 2017 STMicroelectronics. Copyright (C) 2025 Geehy Semiconductor. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file g32r4xx_ddl_adc12.h.