g32r4xx_ddl_adc12.h

Go to the documentation of this file.

 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_ADC12_H
#define G32R4xx_DDL_ADC12_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined (ADC3)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
 
/* Private constants ---------------------------------------------------------*/
 
/* Internal mask for ADC group regular sequencer:                             */
/* To select into literal DDL_ADC12_REG_RANK_x the relevant bits for:            */
/* - sequencer register offset                                                */
/* - sequencer rank bits position into the selected register                  */
 
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC12_SQR1_REGOFFSET                            (0x00000000UL)
#define ADC12_SQR2_REGOFFSET                            (0x00000100UL)
#define ADC12_SQR3_REGOFFSET                            (0x00000200UL)
 
#define ADC12_REG_SQRX_REGOFFSET_MASK                   (ADC12_SQR1_REGOFFSET | ADC12_SQR2_REGOFFSET | ADC12_SQR3_REGOFFSET)
#define ADC12_SQRX_REGOFFSET_POS                        (8UL) /* Position of bits ADC12_SQRx_REGOFFSET in ADC12_REG_SQRX_REGOFFSET_MASK */
#define ADC12_REG_RANK_ID_SQRX_MASK                     (0x1F)
 
/* Definition of ADC group regular sequencer bits information to be inserted  */
/* into ADC group regular sequencer ranks literals definition.                */
#define ADC12_REG_RANK_1_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ1_Pos)
#define ADC12_REG_RANK_2_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ2_Pos)
#define ADC12_REG_RANK_3_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ3_Pos)
#define ADC12_REG_RANK_4_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ4_Pos)
#define ADC12_REG_RANK_5_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ5_Pos)
#define ADC12_REG_RANK_6_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ6_Pos)
#define ADC12_REG_RANK_7_SQRX_BITOFFSET_POS             (ADC_SQR1_SQ7_Pos)
#define ADC12_REG_RANK_8_SQRX_BITOFFSET_POS             (ADC_SQR2_SQ8_Pos)
#define ADC12_REG_RANK_9_SQRX_BITOFFSET_POS             (ADC_SQR2_SQ9_Pos)
#define ADC12_REG_RANK_10_SQRX_BITOFFSET_POS            (ADC_SQR2_SQ10_Pos)
#define ADC12_REG_RANK_11_SQRX_BITOFFSET_POS            (ADC_SQR2_SQ11_Pos)
#define ADC12_REG_RANK_12_SQRX_BITOFFSET_POS            (ADC_SQR2_SQ12_Pos)
#define ADC12_REG_RANK_13_SQRX_BITOFFSET_POS            (ADC_SQR2_SQ13_Pos)
#define ADC12_REG_RANK_14_SQRX_BITOFFSET_POS            (ADC_SQR2_SQ14_Pos)
#define ADC12_REG_RANK_15_SQRX_BITOFFSET_POS            (ADC_SQR3_SQ15_Pos)
#define ADC12_REG_RANK_16_SQRX_BITOFFSET_POS            (ADC_SQR3_SQ16_Pos)
 
/* Internal mask for ADC group injected sequencer:                            */
/* To select into literal DDL_ADC12_INJ_RANK_x the relevant bits for:            */
/* - data register offset                                                     */
/* - sequencer rank bits position into the selected register                  */
 
/* Internal register offset for ADC group injected data register */
/* (offset placed into a spare area of literal definition) */
#define ADC12_JDR1_REGOFFSET                            (0x00000000UL)
#define ADC12_JDR2_REGOFFSET                            (0x00000100UL)
#define ADC12_JDR3_REGOFFSET                            (0x00000200UL)
#define ADC12_JDR4_REGOFFSET                            (0x00000300UL)
 
#define ADC12_INJ_JDRX_REGOFFSET_MASK                   (ADC12_JDR1_REGOFFSET | ADC12_JDR2_REGOFFSET \
                                            | ADC12_JDR3_REGOFFSET | ADC12_JDR4_REGOFFSET)
#define ADC12_INJ_RANK_ID_JSQR_MASK                     (0x1F)
#define ADC12_JDRX_REGOFFSET_POS                        (8UL) /* Position of bits ADC12_JDRx_REGOFFSET in ADC12_INJ_JDRX_REGOFFSET_MASK */
 
/* Definition of ADC group injected sequencer bits information to be inserted */
/* into ADC group injected sequencer ranks literals definition.               */
#define ADC12_INJ_RANK_1_JSQR_BITOFFSET_POS             (ADC_JSQR_JSQ1_Pos)
#define ADC12_INJ_RANK_3_JSQR_BITOFFSET_POS             (ADC_JSQR_JSQ3_Pos)
#define ADC12_INJ_RANK_2_JSQR_BITOFFSET_POS             (ADC_JSQR_JSQ2_Pos)
#define ADC12_INJ_RANK_4_JSQR_BITOFFSET_POS             (ADC_JSQR_JSQ4_Pos)
 
/* Internal mask for ADC group regular trigger:                               */
/* To select into literal DDL_ADC12_REG_TRIG_x the relevant bits for:            */
/* - regular trigger source                                                   */
/* - regular trigger edge                                                     */
#define ADC12_REG_TRIG_EXT_EDGE_DEFAULT                 (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */
 
/* Mask containing trigger source masks for each of possible                  */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC12_REG_TRIG_SOURCE_MASK                      (((DDL_ADC12_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 3UL))  )
 
/* Mask containing trigger edge masks for each of possible                    */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC12_REG_TRIG_EDGE_MASK                        (((DDL_ADC12_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
                                             ((ADC12_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC12_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC12_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
 
/* Definition of ADC group regular trigger bits information.                  */
#define ADC12_REG_TRIG_EXTSEL_BITOFFSET_POS             (ADC_CFGR_EXTSEL_Pos)
#define ADC12_REG_TRIG_EXTEN_BITOFFSET_POS              (ADC_CFGR_EXTEN_Pos)
 
/* Internal mask for ADC group injected trigger:                              */
/* To select into literal DDL_ADC12_INJ_TRIG_x the relevant bits for:            */
/* - injected trigger source                                                  */
/* - injected trigger edge                                                    */
#define ADC12_INJ_TRIG_EXT_EDGE_DEFAULT                 (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */
 
/* Mask containing trigger source masks for each of possible                  */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC12_INJ_TRIG_SOURCE_MASK                      (((DDL_ADC12_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
 
/* Mask containing trigger edge masks for each of possible                    */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC12_INJ_TRIG_EDGE_MASK                        (((DDL_ADC12_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
                                             ((ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
 
/* Definition of ADC group injected trigger bits information.                 */
#define ADC12_INJ_TRIG_EXTSEL_BITOFFSET_POS             (ADC_JSQR_JEXTSEL_Pos)
#define ADC12_INJ_TRIG_EXTEN_BITOFFSET_POS              (ADC_JSQR_JEXTEN_Pos)
 
/* Internal mask for ADC channel:                                             */
/* To select into literal DDL_ADC12_CHANNEL_x the relevant bits for:             */
/* - channel identifier defined by number                                     */
/* - channel identifier defined by bitfield                                   */
/* - channel differentiation between external channels (connected to          */
/*   GPIO pins) and internal channels (connected to internal paths)           */
/* - channel sampling time defined by SMPRx register offset                   */
/*   and SMPx bits positions into SMPRx register                              */
#define ADC12_CHANNEL_ID_NUMBER_MASK                    (ADC_CFGR_AWD1CH)
#define ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS           (ADC_CFGR_AWD1CH_Pos)
#define ADC12_CHANNEL_ID_MASK                           (ADC12_CHANNEL_ID_NUMBER_MASK  \
                                            | ADC12_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC12_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC12_CHANNEL_ID_NUMBER_MASK_POSBIT0            (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC12_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC12_CHANNEL_NUMBER_MASK" in register]) */
 
/* Channel differentiation between external and internal channels */
#define ADC12_CHANNEL_ID_INTERNAL_CH                    (0x80000000UL) /* Marker of internal channel */
#define ADC12_CHANNEL_ID_INTERNAL_CH_2                  (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define ADC12_CHANNEL_ID_INTERNAL_CH_MASK               (ADC12_CHANNEL_ID_INTERNAL_CH | ADC12_CHANNEL_ID_INTERNAL_CH_2)
 
/* Internal register offset for ADC channel sampling time configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC12_SMPR1_REGOFFSET                           (0x00000000UL)
#define ADC12_SMPR2_REGOFFSET                           (0x02000000UL)
#define ADC12_CHANNEL_SMPRX_REGOFFSET_MASK              (ADC12_SMPR1_REGOFFSET | ADC12_SMPR2_REGOFFSET)
#define ADC12_SMPRX_REGOFFSET_POS                       (25UL) /* Position of bits ADC12_SMPRx_REGOFFSET in ADC12_CHANNEL_SMPRX_REGOFFSET_MASK */
 
#define ADC12_CHANNEL_SMPx_BITOFFSET_MASK               (0x01F00000UL)
#define ADC12_CHANNEL_SMPx_BITOFFSET_POS                (20UL)           /* Value equivalent to bitfield "ADC12_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
 
/* Definition of channels ID number information to be inserted into           */
/* channels literals definition.                                              */
#define ADC12_CHANNEL_0_NUMBER                          (0x00000000UL)
#define ADC12_CHANNEL_1_NUMBER                          (ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_2_NUMBER                          (ADC_CFGR_AWD1CH_1)
#define ADC12_CHANNEL_3_NUMBER                          (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_4_NUMBER                          (ADC_CFGR_AWD1CH_2)
#define ADC12_CHANNEL_5_NUMBER                          (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_6_NUMBER                          (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define ADC12_CHANNEL_7_NUMBER                          (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_8_NUMBER                          (ADC_CFGR_AWD1CH_3)
#define ADC12_CHANNEL_9_NUMBER                          (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_10_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
#define ADC12_CHANNEL_11_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_12_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
#define ADC12_CHANNEL_13_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define ADC12_CHANNEL_14_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define ADC12_CHANNEL_15_NUMBER                         (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
 
/* Definition of channels sampling time information to be inserted into       */
/* channels literals definition.                                              */
#define ADC12_CHANNEL_0_SMP                             (ADC12_SMPR1_REGOFFSET | (( 0UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define ADC12_CHANNEL_1_SMP                             (ADC12_SMPR1_REGOFFSET | (( 4UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define ADC12_CHANNEL_2_SMP                             (ADC12_SMPR1_REGOFFSET | (( 8UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define ADC12_CHANNEL_3_SMP                             (ADC12_SMPR1_REGOFFSET | ((12UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define ADC12_CHANNEL_4_SMP                             (ADC12_SMPR1_REGOFFSET | ((16UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define ADC12_CHANNEL_5_SMP                             (ADC12_SMPR1_REGOFFSET | ((20UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define ADC12_CHANNEL_6_SMP                             (ADC12_SMPR1_REGOFFSET | ((24UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define ADC12_CHANNEL_7_SMP                             (ADC12_SMPR1_REGOFFSET | ((28UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define ADC12_CHANNEL_8_SMP                             (ADC12_SMPR2_REGOFFSET | (( 0UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP8" position in register */
#define ADC12_CHANNEL_9_SMP                             (ADC12_SMPR2_REGOFFSET | (( 4UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP9" position in register */
#define ADC12_CHANNEL_10_SMP                            (ADC12_SMPR2_REGOFFSET | (( 8UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define ADC12_CHANNEL_11_SMP                            (ADC12_SMPR2_REGOFFSET | ((12UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define ADC12_CHANNEL_12_SMP                            (ADC12_SMPR2_REGOFFSET | ((16UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define ADC12_CHANNEL_13_SMP                            (ADC12_SMPR2_REGOFFSET | ((20UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define ADC12_CHANNEL_14_SMP                            (ADC12_SMPR2_REGOFFSET | ((24UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define ADC12_CHANNEL_15_SMP                            (ADC12_SMPR2_REGOFFSET | ((28UL) << ADC12_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
/* Internal mask for ADC analog watchdog:                                     */
/* To select into literals DDL_ADC12_AWD_CHANNELx_xxx the relevant bits for:     */
/* (concatenation of multiple bits used in different analog watchdogs,        */
/* - analog watchdog 1: monitored channel defined by number,                  */
/*   selection of ADC group (ADC groups regular and-or injected).             */
/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
/*   selection on groups.                                                     */
 
/* Internal register offset for ADC analog watchdog channel configuration */
#define ADC12_AWD_CR1_REGOFFSET                         (0x00000000UL)
#define ADC12_AWD_CR2_REGOFFSET                         (0x00100000UL)
#define ADC12_AWD_CR3_REGOFFSET                         (0x00200000UL)
 
/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
/* (Set separately as ADC12_AWD_CRX_REGOFFSET to spare 32 bits space */
#define ADC12_AWD_CR12_REGOFFSETGAP_MASK                (ADC_AWD2CR_AWD2CH_0)
#define ADC12_AWD_CR12_REGOFFSETGAP_VAL                 (0x00000010UL)
 
#define ADC12_AWD_CRX_REGOFFSET_MASK                    (ADC12_AWD_CR1_REGOFFSET | ADC12_AWD_CR2_REGOFFSET | ADC12_AWD_CR3_REGOFFSET)
 
#define ADC12_AWD_CR1_CHANNEL_MASK                      (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define ADC12_AWD_CR23_CHANNEL_MASK                     (ADC_AWD2CR_AWD2CH)
#define ADC12_AWD_CR_ALL_CHANNEL_MASK                   (ADC12_AWD_CR1_CHANNEL_MASK | ADC12_AWD_CR23_CHANNEL_MASK)
 
#define ADC12_AWD_CRX_REGOFFSET_POS                     (20UL) /* Position of bits ADC12_AWD_CRx_REGOFFSET in ADC12_AWD_CRX_REGOFFSET_MASK */
 
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC12_AWD_TR1_REGOFFSET                         (ADC12_AWD_CR1_REGOFFSET)
#define ADC12_AWD_TR2_REGOFFSET                         (ADC12_AWD_CR2_REGOFFSET)
#define ADC12_AWD_TR3_REGOFFSET                         (ADC12_AWD_CR3_REGOFFSET)
#define ADC12_AWD_TRX_REGOFFSET_MASK                    (ADC12_AWD_TR1_REGOFFSET | ADC12_AWD_TR2_REGOFFSET | ADC12_AWD_TR3_REGOFFSET)
#define ADC12_AWD_TRX_REGOFFSET_POS                     (ADC12_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC12_SQRx_REGOFFSET in ADC12_AWD_TRX_REGOFFSET_MASK */
#define ADC12_AWD_TRX_BIT_HIGH_MASK                     (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define ADC12_AWD_TRX_BIT_HIGH_POS                      (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */
#define ADC12_AWD_TRX_BIT_HIGH_SHIFT4                   (ADC12_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC12_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
 
/* Internal mask for ADC offset:                                              */
/* Internal register offset for ADC offset number configuration */
#define ADC12_OFR0_REGOFFSET                            (0x00000000UL)
#define ADC12_OFR1_REGOFFSET                            (0x00000001UL)
#define ADC12_OFR2_REGOFFSET                            (0x00000002UL)
#define ADC12_OFR3_REGOFFSET                            (0x00000003UL)
#define ADC12_OFRx_REGOFFSET_MASK                       (ADC12_OFR0_REGOFFSET | ADC12_OFR1_REGOFFSET \
                                          | ADC12_OFR2_REGOFFSET | ADC12_OFR3_REGOFFSET)
 
/* ADC registers bits positions */
#define ADC12_CFGR_AWD1SGL_BITOFFSET_POS                (ADC_CFGR_AWD1SGL_Pos)
#define ADC12_CFGR_AWD1EN_BITOFFSET_POS                 (ADC_CFGR_AWD1EN_Pos)
#define ADC12_CFGR_JAWD1EN_BITOFFSET_POS                (ADC_CFGR_JAWD1EN_Pos)
#define ADC12_TR1_HT1_BITOFFSET_POS                     (ADC_TR1_HT1_Pos)
 
/* ADC registers bits groups */
#define ADC12_CR_BITS_PROPERTY_RS                       (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

 
#define DDL_ADC12_REG_TRIG_SOFTWARE         (0x00000000UL)                                                             
#define DDL_ADC12_REG_TRIG_EXT_TMR1_CC1     (ADC12_REG_TRIG_EXT_EDGE_DEFAULT)                                          
#define DDL_ADC12_REG_TRIG_EXT_TMR1_CC2     (ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC12_REG_TRIG_EXT_TMR1_CC3     (ADC_CFGR_EXTSEL_1 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC12_REG_TRIG_EXT_TMR2_CC2     (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC12_REG_TRIG_EXT_TMR3_TRGO    (ADC_CFGR_EXTSEL_2 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC12_REG_TRIG_EXT_TMR4_CC4     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC12_REG_TRIG_EXT_EINT_LINE11  (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC12_REG_TRIG_EXT_EDGE_DEFAULT)  

#define DDL_ADC12_REG_TRIG_EXT_RISING   (ADC_CFGR_EXTEN_0)  
#define DDL_ADC12_REG_TRIG_EXT_DISABLE  (0x00000000UL)      

#define DDL_ADC12_REG_SEQ_SCAN_DISABLE         (0x00000000UL)                                                   
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_2RANKS   (                                             ADC_SQR1_RL_0)     
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_3RANKS   (                              ADC_SQR1_RL_1               )     
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_4RANKS   (                              ADC_SQR1_RL_1 | ADC_SQR1_RL_0)    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_5RANKS   (               ADC_SQR1_RL_2                              )     
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_6RANKS   (               ADC_SQR1_RL_2                | ADC_SQR1_RL_0)    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_7RANKS   (               ADC_SQR1_RL_2 | ADC_SQR1_RL_1               )    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_8RANKS   (               ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)   
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_9RANKS   (ADC_SQR1_RL_3                                              )    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_10RANKS  (ADC_SQR1_RL_3                               | ADC_SQR1_RL_0)    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_11RANKS  (ADC_SQR1_RL_3                | ADC_SQR1_RL_1               )    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_12RANKS  (ADC_SQR1_RL_3                | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)   
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_13RANKS  (ADC_SQR1_RL_3 | ADC_SQR1_RL_2                              )    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_14RANKS  (ADC_SQR1_RL_3 | ADC_SQR1_RL_2               | ADC_SQR1_RL_0)    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_15RANKS  (ADC_SQR1_RL_3 | ADC_SQR1_RL_2               | ADC_SQR1_RL_1)    
#define DDL_ADC12_REG_SEQ_SCAN_ENABLE_16RANKS  (ADC_SQR1_RL_3 | ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)  

#define DDL_ADC12_REG_SEQ_DISCONT_DISABLE  (0x00000000UL)                                                                    
#define DDL_ADC12_REG_SEQ_DISCONT_1RANK    (                                                               ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_2RANKS   (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_3RANKS   (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_4RANKS   (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_7RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN)  
#define DDL_ADC12_REG_SEQ_DISCONT_8RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  

#define DDL_ADC12_REG_RANK_1   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_1_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_2   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_2_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_3   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_3_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_4   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_4_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_5   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_5_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_6   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_6_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_7   (ADC12_SQR1_REGOFFSET | ADC12_REG_RANK_7_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_8   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_8_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_9   (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_9_SQRX_BITOFFSET_POS)   
#define DDL_ADC12_REG_RANK_10  (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_10_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_11  (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_11_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_12  (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_12_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_13  (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_13_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_14  (ADC12_SQR2_REGOFFSET | ADC12_REG_RANK_14_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_15  (ADC12_SQR3_REGOFFSET | ADC12_REG_RANK_15_SQRX_BITOFFSET_POS)  
#define DDL_ADC12_REG_RANK_16  (ADC12_SQR3_REGOFFSET | ADC12_REG_RANK_16_SQRX_BITOFFSET_POS)  

#define DDL_ADC12_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                   
#define DDL_ADC12_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0)  
#define DDL_ADC12_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                )  
#define DDL_ADC12_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)  

#define DDL_ADC12_INJ_SEQ_DISCONT_DISABLE  (0x00000000UL)      
#define DDL_ADC12_INJ_SEQ_DISCONT_1RANK    (ADC_CFGR_JDISCEN)  
 
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)

typedef struct
{
  uint32_t DataAlignment;  
 
} DDL_ADC12_InitTypeDef;

typedef struct
{
  uint32_t TriggerSource;     
 
  uint32_t SequencerLength;   
 
  uint32_t SequencerDiscont;  
 
  uint32_t ContinuousMode;    
 
  uint32_t DMATransfer;       
 
} DDL_ADC12_REG_InitTypeDef;

typedef struct
{
  uint32_t TriggerSource;     
 
  uint32_t SequencerLength;   
 
  uint32_t SequencerDiscont;  
 
  uint32_t TrigAuto;          
 
} DDL_ADC12_INJ_InitTypeDef;

#endif /* USE_FULL_DDL_DRIVER */
 
/* Private macros ------------------------------------------------------------*/
/* List of ADC registers intended to be used (most commonly) with             */
/* DMA transfer.                                                              */
/* Refer to function @ref DDL_ADC12_DMA_GetRegAddr().                            */
#define DDL_ADC12_DMA_REG_REGULAR_DATA  (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by DDL function @ref DDL_ADC12_REG_ReadConversionData32() and other functions @ref DDL_ADC12_REG_ReadConversionDatax() */

#define DDL_ADC12_JOFFSET_1  ADC12_OFR0_REGOFFSET  
#define DDL_ADC12_JOFFSET_2  ADC12_OFR1_REGOFFSET  
#define DDL_ADC12_JOFFSET_3  ADC12_OFR2_REGOFFSET  
#define DDL_ADC12_JOFFSET_4  ADC12_OFR3_REGOFFSET  

#define DDL_ADC12_CHANNEL_0   (ADC12_CHANNEL_0_NUMBER  | ADC12_CHANNEL_0_SMP)   
#define DDL_ADC12_CHANNEL_1   (ADC12_CHANNEL_1_NUMBER  | ADC12_CHANNEL_1_SMP)   
#define DDL_ADC12_CHANNEL_2   (ADC12_CHANNEL_2_NUMBER  | ADC12_CHANNEL_2_SMP)   
#define DDL_ADC12_CHANNEL_3   (ADC12_CHANNEL_3_NUMBER  | ADC12_CHANNEL_3_SMP)   
#define DDL_ADC12_CHANNEL_4   (ADC12_CHANNEL_4_NUMBER  | ADC12_CHANNEL_4_SMP)   
#define DDL_ADC12_CHANNEL_5   (ADC12_CHANNEL_5_NUMBER  | ADC12_CHANNEL_5_SMP)   
#define DDL_ADC12_CHANNEL_6   (ADC12_CHANNEL_6_NUMBER  | ADC12_CHANNEL_6_SMP)   
#define DDL_ADC12_CHANNEL_7   (ADC12_CHANNEL_7_NUMBER  | ADC12_CHANNEL_7_SMP)   
#define DDL_ADC12_CHANNEL_8   (ADC12_CHANNEL_8_NUMBER  | ADC12_CHANNEL_8_SMP)   
#define DDL_ADC12_CHANNEL_9   (ADC12_CHANNEL_9_NUMBER  | ADC12_CHANNEL_9_SMP)   
#define DDL_ADC12_CHANNEL_10  (ADC12_CHANNEL_10_NUMBER | ADC12_CHANNEL_10_SMP)  
#define DDL_ADC12_CHANNEL_11  (ADC12_CHANNEL_11_NUMBER | ADC12_CHANNEL_11_SMP)  
#define DDL_ADC12_CHANNEL_12  (ADC12_CHANNEL_12_NUMBER | ADC12_CHANNEL_12_SMP)  
#define DDL_ADC12_CHANNEL_13  (ADC12_CHANNEL_13_NUMBER | ADC12_CHANNEL_13_SMP)  
#define DDL_ADC12_CHANNEL_14  (ADC12_CHANNEL_14_NUMBER | ADC12_CHANNEL_14_SMP)  
#define DDL_ADC12_CHANNEL_15  (ADC12_CHANNEL_15_NUMBER | ADC12_CHANNEL_15_SMP)  

#define DDL_ADC12_REG_CONV_SINGLE      (0x00000000UL)   
#define DDL_ADC12_REG_CONV_CONTINUOUS  (ADC_CFGR_CONT)  

#define DDL_ADC12_REG_DMA_TRANSFER_DISABLE  (0x00000000UL)                      
#define DDL_ADC12_REG_DMA_TRANSFER_ENABLE   (                  ADC_CFGR_DMAEN)  

#define DDL_ADC12_INJ_TRIG_SOFTWARE         (0x00000000UL)                                                               
#define DDL_ADC12_INJ_TRIG_EXT_TMR1_TRGO    (ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)                                            
#define DDL_ADC12_INJ_TRIG_EXT_TMR1_CC4     (ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC12_INJ_TRIG_EXT_TMR2_TRGO    (ADC_JSQR_JEXTSEL_1 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC12_INJ_TRIG_EXT_TMR2_CC1     (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC12_INJ_TRIG_EXT_TMR3_CC4     (ADC_JSQR_JEXTSEL_2 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC12_INJ_TRIG_EXT_TMR4_TRGO    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC12_INJ_TRIG_EXT_EINT_LINE15  (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC12_INJ_TRIG_EXT_EDGE_DEFAULT)  

#define DDL_ADC12_INJ_TRIG_EXT_RISING   (                    ADC_JSQR_JEXTEN_0)  
#define DDL_ADC12_INJ_TRIG_EXT_DISABLE  (0x00000000UL)                           

#define DDL_ADC12_INJ_RANK_1  (ADC12_JDR1_REGOFFSET | ADC12_INJ_RANK_1_JSQR_BITOFFSET_POS)  
#define DDL_ADC12_INJ_RANK_2  (ADC12_JDR2_REGOFFSET | ADC12_INJ_RANK_2_JSQR_BITOFFSET_POS)  
#define DDL_ADC12_INJ_RANK_3  (ADC12_JDR3_REGOFFSET | ADC12_INJ_RANK_3_JSQR_BITOFFSET_POS)  
#define DDL_ADC12_INJ_RANK_4  (ADC12_JDR4_REGOFFSET | ADC12_INJ_RANK_4_JSQR_BITOFFSET_POS)  

#define DDL_ADC12_INJ_TRIG_INDEPENDENT       (0x00000000UL)    
#define DDL_ADC12_INJ_TRIG_FROM_GRP_REGULAR  (ADC_CFGR_JAUTO)  

#define DDL_ADC12_SAMPLINGTIME_7CYCLES    (0x00000000)
#define DDL_ADC12_SAMPLINGTIME_16CYCLES   (ADC_SMPR1_SMP0_0)
#define DDL_ADC12_SAMPLINGTIME_27CYCLES   (ADC_SMPR1_SMP0_1)
#define DDL_ADC12_SAMPLINGTIME_32CYCLES   (ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC12_SAMPLINGTIME_67CYCLES   (ADC_SMPR1_SMP0_2)
#define DDL_ADC12_SAMPLINGTIME_96CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define DDL_ADC12_SAMPLINGTIME_128CYCLES  (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define DDL_ADC12_SAMPLINGTIME_256CYCLES  (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)


#define DDL_ADC12_AWD1  (ADC12_AWD_CR1_CHANNEL_MASK  | ADC12_AWD_CR1_REGOFFSET)  

#define DDL_ADC12_AWD_DISABLE               (0x00000000UL)                                                                                            
#define DDL_ADC12_AWD_ALL_CHANNELS_REG      (ADC_CFGR_AWD1EN                                                                                   )      
#define DDL_ADC12_AWD_ALL_CHANNELS_INJ      (ADC_CFGR_JAWD1EN                                                                                  )      
#define DDL_ADC12_AWD_ALL_CHANNELS_REG_INJ  (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                                                                )      
#define DDL_ADC12_AWD_CHANNEL_0_REG         ((DDL_ADC12_CHANNEL_0  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_0_INJ         ((DDL_ADC12_CHANNEL_0  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_0_REG_INJ     ((DDL_ADC12_CHANNEL_0  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_1_REG         ((DDL_ADC12_CHANNEL_1  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_1_INJ         ((DDL_ADC12_CHANNEL_1  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_1_REG_INJ     ((DDL_ADC12_CHANNEL_1  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_2_REG         ((DDL_ADC12_CHANNEL_2  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_2_INJ         ((DDL_ADC12_CHANNEL_2  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_2_REG_INJ     ((DDL_ADC12_CHANNEL_2  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_3_REG         ((DDL_ADC12_CHANNEL_3  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_3_INJ         ((DDL_ADC12_CHANNEL_3  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_3_REG_INJ     ((DDL_ADC12_CHANNEL_3  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_4_REG         ((DDL_ADC12_CHANNEL_4  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_4_INJ         ((DDL_ADC12_CHANNEL_4  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_4_REG_INJ     ((DDL_ADC12_CHANNEL_4  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_5_REG         ((DDL_ADC12_CHANNEL_5  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_5_INJ         ((DDL_ADC12_CHANNEL_5  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_5_REG_INJ     ((DDL_ADC12_CHANNEL_5  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_6_REG         ((DDL_ADC12_CHANNEL_6  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_6_INJ         ((DDL_ADC12_CHANNEL_6  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_6_REG_INJ     ((DDL_ADC12_CHANNEL_6  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_7_REG         ((DDL_ADC12_CHANNEL_7  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_7_INJ         ((DDL_ADC12_CHANNEL_7  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_7_REG_INJ     ((DDL_ADC12_CHANNEL_7  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_8_REG         ((DDL_ADC12_CHANNEL_8  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_8_INJ         ((DDL_ADC12_CHANNEL_8  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_8_REG_INJ     ((DDL_ADC12_CHANNEL_8  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_9_REG         ((DDL_ADC12_CHANNEL_9  & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_9_INJ         ((DDL_ADC12_CHANNEL_9  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_9_REG_INJ     ((DDL_ADC12_CHANNEL_9  & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_10_REG        ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_10_INJ        ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_10_REG_INJ    ((DDL_ADC12_CHANNEL_10 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_11_REG        ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_11_INJ        ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_11_REG_INJ    ((DDL_ADC12_CHANNEL_11 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_12_REG        ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_12_INJ        ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_12_REG_INJ    ((DDL_ADC12_CHANNEL_12 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_13_REG        ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_13_INJ        ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC12_AWD_CHANNEL_13_REG_INJ    ((DDL_ADC12_CHANNEL_13 & ADC12_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  

#define DDL_ADC12_AWD_THRESHOLD_HIGH       (ADC_TR1_HT1              )  
#define DDL_ADC12_AWD_THRESHOLD_LOW        (              ADC_TR1_LT1)  
#define DDL_ADC12_AWD_THRESHOLDS_HIGH_LOW  (ADC_TR1_HT1 | ADC_TR1_LT1)  

#define DDL_ADC12_FLAG_EOC   ADC_ISR_EOC   
#define DDL_ADC12_FLAG_EOS   ADC_ISR_EOS   
#define DDL_ADC12_FLAG_JEOC  ADC_ISR_JEOC  
#define DDL_ADC12_FLAG_JEOS  ADC_ISR_JEOS  
#define DDL_ADC12_FLAG_AWD1  ADC_ISR_AWD1  

#define DDL_ADC12_IT_EOC   ADC_IER_EOCIE   
#define DDL_ADC12_IT_EOS   ADC_IER_EOSIE   
#define DDL_ADC12_IT_JEOC  ADC_IER_JEOCIE  
#define DDL_ADC12_IT_JEOS  ADC_IER_JEOSIE  
#define DDL_ADC12_IT_AWD1  ADC_IER_AWD1IE  

#define DDL_ADC12_ALIGNMENT_LEFT   ADC_CFGR_ALIGN
#define DDL_ADC12_ALIGNMENT_RIGHT  (0x00000000UL)

 
/* Private macros ------------------------------------------------------------*/

#define __ADC12_PTR_REG_OFFSET(__REG__,                 __REG_OFFFSET__)                         \
  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

#define __DDL_ADC12_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)  ((uint32_t)((__CHANNEL__ & ADC_CFGR_AWD1CH_Msk) >> ADC_CFGR_AWD1CH_Pos))

 
/* Exported functions --------------------------------------------------------*/
/* Note: DDL ADC functions to set DMA transfer are located into sections of    */
/*       configuration of ADC instance, groups and multimode (if available):  */
/*       @ref DDL_ADC12_REG_SetDMATransfer(), ...                                */

__STATIC_INLINE uint32_t DDL_ADC12_DMA_GetRegAddr(ADC12_TypeDef *ADCx, uint32_t Register)
{
  /* Prevent unused argument(s) compilation warning */
  (void)(Register);
 
  /* Retrieve address of register DR */
  return (uint32_t) &(ADCx->DR);
}



__STATIC_INLINE void DDL_ADC12_INJ_SetOffset(ADC12_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
{
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->JOFFSET1, Offsety);
 
  MODIFY_REG(*preg,
             ADC_JOFFSET1_JOFFSET1,
             OffsetLevel);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetOffset(ADC12_TypeDef *ADCx, uint32_t Offsety)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->JOFFSET1, Offsety);
 
  return (uint32_t)READ_BIT(*preg, ADC_JOFFSET1_JOFFSET1);
}


__STATIC_INLINE void DDL_ADC12_REG_SetTriggerSource(ADC12_TypeDef *ADCx, uint32_t TriggerSource)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetTriggerSource(ADC12_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_IsTriggerSourceSWStart(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (DDL_ADC12_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC12_REG_SetTriggerEdge(ADC12_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetTriggerEdge(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
}

__STATIC_INLINE void DDL_ADC12_REG_SetSequencerLength(ADC12_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  MODIFY_REG(ADCx->SQR1, ADC_SQR1_RL, SequencerNbRanks);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetSequencerLength(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_RL));
}

__STATIC_INLINE void DDL_ADC12_REG_SetSequencerDiscont(ADC12_TypeDef *ADCx, uint32_t SeqDiscont)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetSequencerDiscont(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
}

__STATIC_INLINE void DDL_ADC12_REG_SetSequencerRanks(ADC12_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register and register position depending on parameter "Rank".         */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC12_REG_SQRX_REGOFFSET_MASK) >> ADC12_SQRX_REGOFFSET_POS));
 
  MODIFY_REG(*preg,
             ADC12_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC12_REG_RANK_ID_SQRX_MASK),
             ((Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC12_REG_RANK_ID_SQRX_MASK));
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetSequencerRanks(ADC12_TypeDef *ADCx, uint32_t Rank)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC12_REG_SQRX_REGOFFSET_MASK) >> ADC12_SQRX_REGOFFSET_POS));
 
  return (uint32_t)((READ_BIT(*preg,
                              ADC12_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC12_REG_RANK_ID_SQRX_MASK))
                     >> (Rank & ADC12_REG_RANK_ID_SQRX_MASK)) << ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS
                   );
}

__STATIC_INLINE void DDL_ADC12_REG_SetContinuousMode(ADC12_TypeDef *ADCx, uint32_t Continuous)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetContinuousMode(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
}

__STATIC_INLINE void DDL_ADC12_REG_SetDMATransfer(ADC12_TypeDef *ADCx, uint32_t DMATransfer)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN, DMATransfer);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_GetDMATransfer(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN));
}


__STATIC_INLINE void DDL_ADC12_INJ_SetTriggerSource(ADC12_TypeDef *ADCx, uint32_t TriggerSource)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetTriggerSource(ADC12_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_IsTriggerSourceSWStart(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (DDL_ADC12_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC12_INJ_SetTriggerEdge(ADC12_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetTriggerEdge(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}

__STATIC_INLINE void DDL_ADC12_INJ_SetSequencerLength(ADC12_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetSequencerLength(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}

__STATIC_INLINE void DDL_ADC12_INJ_SetSequencerDiscont(ADC12_TypeDef *ADCx, uint32_t SeqDiscont)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetSequencerDiscont(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
}

__STATIC_INLINE void DDL_ADC12_INJ_SetSequencerRanks(ADC12_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register depending on parameter "Rank".                               */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  MODIFY_REG(ADCx->JSQR,
             (ADC12_CHANNEL_ID_NUMBER_MASK >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC12_INJ_RANK_ID_JSQR_MASK),
             ((Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC12_INJ_RANK_ID_JSQR_MASK));
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetSequencerRanks(ADC12_TypeDef *ADCx, uint32_t Rank)
{
  return (uint32_t)((READ_BIT(ADCx->JSQR,
                              (ADC12_CHANNEL_ID_NUMBER_MASK >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC12_INJ_RANK_ID_JSQR_MASK))
                     >> (Rank & ADC12_INJ_RANK_ID_JSQR_MASK)) << ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS
                   );
}

__STATIC_INLINE void DDL_ADC12_INJ_SetTrigAuto(ADC12_TypeDef *ADCx, uint32_t TrigAuto)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_GetTrigAuto(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
}

__STATIC_INLINE void DDL_ADC12_INJ_ConfigQueueContext(ADC12_TypeDef *ADCx,
                                                   uint32_t TriggerSource,
                                                   uint32_t ExternalTriggerEdge,
                                                   uint32_t SequencerNbRanks,
                                                   uint32_t Rank1_Channel,
                                                   uint32_t Rank2_Channel,
                                                   uint32_t Rank3_Channel,
                                                   uint32_t Rank4_Channel)
{
  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
  /* in register depending on literal "DDL_ADC12_INJ_RANK_x".                    */
  /* Parameters "Rankx_Channel" and "DDL_ADC12_INJ_RANK_x" are used with masks   */
  /* because containing other bits reserved for other purpose.                */
  /* If parameter "TriggerSource" is set to SW start, then parameter          */
  /* "ExternalTriggerEdge" is discarded.                                      */
  uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != DDL_ADC12_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
  MODIFY_REG(ADCx->JSQR,
             ADC_JSQR_JEXTSEL |
             ADC_JSQR_JEXTEN  |
             ADC_JSQR_JSQ4    |
             ADC_JSQR_JSQ3    |
             ADC_JSQR_JSQ2    |
             ADC_JSQR_JSQ1    |
             ADC_JSQR_JL,
             (TriggerSource & ADC_JSQR_JEXTSEL)          |
             (ExternalTriggerEdge * (is_trigger_not_sw)) |
             (((Rank4_Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC12_INJ_RANK_4 & ADC12_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank3_Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC12_INJ_RANK_3 & ADC12_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank2_Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC12_INJ_RANK_2 & ADC12_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank1_Channel & ADC12_CHANNEL_ID_NUMBER_MASK) >> ADC12_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC12_INJ_RANK_1 & ADC12_INJ_RANK_ID_JSQR_MASK)) |
             SequencerNbRanks
            );
}


__STATIC_INLINE void DDL_ADC12_SetChannelSamplingTime(ADC12_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
  /* Set bits with content of parameter "SamplingTime" with bits position     */
  /* in register and register position depending on parameter "Channel".      */
  /* Parameter "Channel" is used with masks because containing                */
  /* other bits reserved for other purpose.                                   */
 
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC12_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC12_SMPRX_REGOFFSET_POS));
  MODIFY_REG(*preg,
             ADC_SMPR1_SMP0 << ((Channel & ADC12_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC12_CHANNEL_SMPx_BITOFFSET_POS),
             SamplingTime   << ((Channel & ADC12_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC12_CHANNEL_SMPx_BITOFFSET_POS));
}

__STATIC_INLINE uint32_t DDL_ADC12_GetChannelSamplingTime(ADC12_TypeDef *ADCx, uint32_t Channel)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC12_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC12_SMPRX_REGOFFSET_POS));
  return (uint32_t)(READ_BIT(*preg,
                             ADC_SMPR1_SMP0 << ((Channel & ADC12_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC12_CHANNEL_SMPx_BITOFFSET_POS))
                    >> ((Channel & ADC12_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC12_CHANNEL_SMPx_BITOFFSET_POS)
                   );
}


__STATIC_INLINE void DDL_ADC12_SetAnalogWDMonitChannels(ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
  /* in register and register position depending on parameter "AWDy".         */
  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC12_AWD_CRX_REGOFFSET_MASK) >> ADC12_AWD_CRX_REGOFFSET_POS)
                                             + ((AWDy & ADC12_AWD_CR12_REGOFFSETGAP_MASK) * ADC12_AWD_CR12_REGOFFSETGAP_VAL));
 
  MODIFY_REG(*preg,
             (AWDy & ADC12_AWD_CR_ALL_CHANNEL_MASK),
             AWDChannelGroup & AWDy);
}

__STATIC_INLINE uint32_t DDL_ADC12_GetAnalogWDMonitChannels(ADC12_TypeDef *ADCx, uint32_t AWDy)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC12_AWD_CRX_REGOFFSET_MASK) >> ADC12_AWD_CRX_REGOFFSET_POS)
                                                   + ((AWDy & ADC12_AWD_CR12_REGOFFSETGAP_MASK) * ADC12_AWD_CR12_REGOFFSETGAP_VAL));
 
  uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC12_AWD_CR_ALL_CHANNEL_MASK);
 
  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
  /* (parameter value DDL_ADC12_AWD_DISABLE).                                    */
  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
  /* or a single channel.                                                     */
 
  return AnalogWDMonitChannels;
}

__STATIC_INLINE void DDL_ADC12_ConfigAnalogWDThresholds(ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
                                                     uint32_t AWDThresholdLowValue)
{
  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
  /* position in register and register position depending on parameter        */
  /* "AWDy".                                                                  */
  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC12_AWD_TRX_REGOFFSET_MASK) >> ADC12_AWD_TRX_REGOFFSET_POS));
 
  MODIFY_REG(*preg,
             ADC_TR1_HT1 | ADC_TR1_LT1,
             (AWDThresholdHighValue << ADC12_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
}

__STATIC_INLINE void DDL_ADC12_SetAnalogWDThresholds(ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
                                                  uint32_t AWDThresholdValue)
{
  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
  /* position in register and register position depending on parameters       */
  /* "AWDThresholdsHighLow" and "AWDy".                                       */
  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->TR1,
                                             ((AWDy & ADC12_AWD_TRX_REGOFFSET_MASK) >> ADC12_AWD_TRX_REGOFFSET_POS));
 
  MODIFY_REG(*preg,
             AWDThresholdsHighLow,
             AWDThresholdValue << ((AWDThresholdsHighLow & ADC12_AWD_TRX_BIT_HIGH_MASK) >> ADC12_AWD_TRX_BIT_HIGH_SHIFT4));
}

__STATIC_INLINE uint32_t DDL_ADC12_GetAnalogWDThresholds(ADC12_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->TR1,
                                                   ((AWDy & ADC12_AWD_TRX_REGOFFSET_MASK) >> ADC12_AWD_TRX_REGOFFSET_POS));
 
  return (uint32_t)(READ_BIT(*preg,
                             (AWDThresholdsHighLow | ADC_TR1_LT1))
                    >> (((AWDThresholdsHighLow & ADC12_AWD_TRX_BIT_HIGH_MASK) >> ADC12_AWD_TRX_BIT_HIGH_SHIFT4)
                        & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
}


__STATIC_INLINE void DDL_ADC12_Enable(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADEN,
             ADC_CR_ADEN);
}

__STATIC_INLINE void DDL_ADC12_Disable(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADEN,
             0);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabled(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC12_SetDataAlignment(ADC12_TypeDef *ADCx, uint32_t Alignment)
{
    MODIFY_REG(ADCx->CFGR,
             ADC_CFGR_ALIGN,
             Alignment);
}

__STATIC_INLINE uint32_t DDL_ADC12_GetDataAlignment(ADC12_TypeDef *ADCx)
{
    return (uint32_t)READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN);
}


__STATIC_INLINE void DDL_ADC12_REG_StartConversion(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADSTART,
             ADC_CR_ADSTART);
}

__STATIC_INLINE void DDL_ADC12_REG_StopConversion(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADSTP,
             ADC_CR_ADSTP);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_IsConversionOngoing(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_IsStopConversionOngoing(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_REG_ReadConversionData32(ADC12_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA | ADC_DR_ADC2RDATA));
}



__STATIC_INLINE void DDL_ADC12_INJ_StartConversion(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_JADSTART,
             ADC_CR_JADSTART);
}

__STATIC_INLINE void DDL_ADC12_INJ_StopConversion(ADC12_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_JADSTP,
             ADC_CR_JADSTP);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_IsConversionOngoing(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_IsStopConversionOngoing(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_INJ_ReadConversionData32(ADC12_TypeDef *ADCx, uint32_t Rank)
{
  const __IO uint32_t *preg = __ADC12_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC12_INJ_JDRX_REGOFFSET_MASK) >> ADC12_JDRX_REGOFFSET_POS));
 
  return (uint32_t)(READ_BIT(*preg,
                             ADC_JDR1_JDATA)
                   );
}



__STATIC_INLINE uint32_t DDL_ADC12_IsActiveFlag_EOC(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC12_FLAG_EOC) == (DDL_ADC12_FLAG_EOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsActiveFlag_EOS(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC12_FLAG_EOS) == (DDL_ADC12_FLAG_EOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsActiveFlag_JEOC(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC12_FLAG_JEOC) == (DDL_ADC12_FLAG_JEOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsActiveFlag_JEOS(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC12_FLAG_JEOS) == (DDL_ADC12_FLAG_JEOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsActiveFlag_AWD1(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC12_FLAG_AWD1) == (DDL_ADC12_FLAG_AWD1)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC12_ClearFlag_EOC(ADC12_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC12_FLAG_EOC);
}

__STATIC_INLINE void DDL_ADC12_ClearFlag_EOS(ADC12_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC12_FLAG_EOS);
}

__STATIC_INLINE void DDL_ADC12_ClearFlag_JEOC(ADC12_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC12_FLAG_JEOC);
}

__STATIC_INLINE void DDL_ADC12_ClearFlag_JEOS(ADC12_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC12_FLAG_JEOS);
}

__STATIC_INLINE void DDL_ADC12_ClearFlag_AWD1(ADC12_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC12_FLAG_AWD1);
}



__STATIC_INLINE void DDL_ADC12_EnableIT_EOC(ADC12_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC12_IT_EOC);
}

__STATIC_INLINE void DDL_ADC12_EnableIT_EOS(ADC12_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC12_IT_EOS);
}

__STATIC_INLINE void DDL_ADC12_EnableIT_JEOC(ADC12_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC12_IT_JEOC);
}

__STATIC_INLINE void DDL_ADC12_EnableIT_JEOS(ADC12_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC12_IT_JEOS);
}

__STATIC_INLINE void DDL_ADC12_EnableIT_AWD1(ADC12_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC12_IT_AWD1);
}

__STATIC_INLINE void DDL_ADC12_DisableIT_EOC(ADC12_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC12_IT_EOC);
}

__STATIC_INLINE void DDL_ADC12_DisableIT_EOS(ADC12_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC12_IT_EOS);
}

__STATIC_INLINE void DDL_ADC12_DisableIT_JEOC(ADC12_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC12_IT_JEOC);
}

__STATIC_INLINE void DDL_ADC12_DisableIT_JEOS(ADC12_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC12_IT_JEOS);
}

__STATIC_INLINE void DDL_ADC12_DisableIT_AWD1(ADC12_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC12_IT_AWD1);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabledIT_EOC(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC12_IT_EOC) == (DDL_ADC12_IT_EOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabledIT_EOS(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC12_IT_EOS) == (DDL_ADC12_IT_EOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabledIT_JEOC(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC12_IT_JEOC) == (DDL_ADC12_IT_JEOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabledIT_JEOS(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC12_IT_JEOS) == (DDL_ADC12_IT_JEOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC12_IsEnabledIT_AWD1(ADC12_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC12_IT_AWD1) == (DDL_ADC12_IT_AWD1)) ? 1UL : 0UL);
}

 
#if defined(USE_FULL_DDL_DRIVER)
 
/* De-initialization of ADC instance, ADC group regular and ADC group injected */
/* (availability of ADC group injected depends on G32R4 families) */
ErrorStatus DDL_ADC12_DeInit(ADC12_TypeDef *ADCx);
 
/* Initialization of some features of ADC instance */
ErrorStatus DDL_ADC12_Init(ADC12_TypeDef *ADCx, DDL_ADC12_InitTypeDef *ADC_InitStruct);
void        DDL_ADC12_StructInit(DDL_ADC12_InitTypeDef *ADC_InitStruct);
 
/* Initialization of some features of ADC instance and ADC group regular */
ErrorStatus DDL_ADC12_REG_Init(ADC12_TypeDef *ADCx, DDL_ADC12_REG_InitTypeDef *ADC_REG_InitStruct);
void        DDL_ADC12_REG_StructInit(DDL_ADC12_REG_InitTypeDef *ADC_REG_InitStruct);
 
/* Initialization of some features of ADC instance and ADC group injected */
ErrorStatus DDL_ADC12_INJ_Init(ADC12_TypeDef *ADCx, DDL_ADC12_INJ_InitTypeDef *ADC_INJ_InitStruct);
void        DDL_ADC12_INJ_StructInit(DDL_ADC12_INJ_InitTypeDef *ADC_INJ_InitStruct);

#endif /* USE_FULL_DDL_DRIVER */



 
#endif /* defined (ADC3) */
 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4XX_DDL_ADC12_H */