G32R430 Device Driver Layer v1.0.4
G32R4xx Device Driver Layer API Reference
Data Structures | Macros | Functions
g32r4xx_ddl_adc16.h File Reference

Header file of ADC DDL module. More...

#include "g32r4xx.h"

Go to the source code of this file.

Data Structures

struct  DDL_ADC16_InitTypeDef
 Structure definition of some features of ADC instance. More...
struct  DDL_ADC16_REG_InitTypeDef
 Structure definition of some features of ADC group regular. More...
struct  DDL_ADC16_INJ_InitTypeDef
 Structure definition of some features of ADC group injected. More...

Macros

#define ADC_SQR1_REGOFFSET   (0x00000000UL)
#define ADC_SQR2_REGOFFSET   (0x00000100UL)
#define ADC_REG_SQRX_REGOFFSET_MASK   (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS   (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK   (0x1F)
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ1_Pos)
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ2_Pos)
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ3_Pos)
#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ4_Pos)
#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ5_Pos)
#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ6_Pos)
#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS   (ADC_SQR1_SQ7_Pos)
#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ8_Pos)
#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ9_Pos)
#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ10_Pos)
#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ11_Pos)
#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS   (ADC_SQR2_SQ12_Pos)
#define ADC_JDR1_REGOFFSET   (0x00000000UL)
#define ADC_JDR2_REGOFFSET   (0x00000100UL)
#define ADC_JDR3_REGOFFSET   (0x00000200UL)
#define ADC_JDR4_REGOFFSET   (0x00000300UL)
#define ADC_INJ_JDRX_REGOFFSET_MASK
#define ADC_INJ_RANK_ID_JSQR_MASK   (0x1F)
#define ADC_JDRX_REGOFFSET_POS   (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ1_Pos)
#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ2_Pos)
#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ3_Pos)
#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS   (ADC_JSQR_JSQ4_Pos)
#define ADC_REG_TRIG_EXT_EDGE_DEFAULT   (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */
#define ADC_REG_TRIG_SOURCE_MASK
#define ADC_REG_TRIG_EDGE_MASK
#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS   (ADC_CFGR_EXTSEL_Pos)
#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT   (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */
#define ADC_INJ_TRIG_SOURCE_MASK
#define ADC_INJ_TRIG_EDGE_MASK
#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS   (ADC_JSQR_JEXTSEL_Pos)
#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
#define ADC16_CFGR_AWD1CH   (0x7UL << ADC_CFGR_AWD1CH_Pos)
#define ADC_CHANNEL_ID_NUMBER_MASK   (ADC16_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK   (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS   (ADC_CFGR_AWD1CH_Pos)
#define ADC_CHANNEL_ID_MASK
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0   (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define ADC_CHANNEL_ID_INTERNAL_CH   (0x80000000UL) /* Marker of internal channel */
#define ADC_CHANNEL_ID_INTERNAL_CH_2   (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define ADC_CHANNEL_ID_INTERNAL_CH_MASK   (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define ADC_SMPR1_REGOFFSET   (0x00000000UL)
#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET)
#define ADC_SMPRX_REGOFFSET_POS   (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define ADC_CHANNEL_SMPx_BITOFFSET_MASK   (0x01F00000UL)
#define ADC_CHANNEL_SMPx_BITOFFSET_POS   (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define ADC_CHANNEL_0_NUMBER   (0x00000000UL)
#define ADC_CHANNEL_1_NUMBER   (ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_2_NUMBER   (ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_3_NUMBER   (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_4_NUMBER   (ADC_CFGR_AWD1CH_2)
#define ADC_CHANNEL_5_NUMBER   (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_0_BITFIELD   (ADC_AWD2CR_AWD2CH_0)
#define ADC_CHANNEL_1_BITFIELD   (ADC_AWD2CR_AWD2CH_1)
#define ADC_CHANNEL_2_BITFIELD   (ADC_AWD2CR_AWD2CH_2)
#define ADC_CHANNEL_3_BITFIELD   (ADC_AWD2CR_AWD2CH_3)
#define ADC_CHANNEL_4_BITFIELD   (ADC_AWD2CR_AWD2CH_4)
#define ADC_CHANNEL_5_BITFIELD   (ADC_AWD2CR_AWD2CH_5)
#define ADC_CHANNEL_0_SMP   (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define ADC_CHANNEL_1_SMP   (ADC_SMPR1_REGOFFSET | (( 4UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define ADC_CHANNEL_2_SMP   (ADC_SMPR1_REGOFFSET | (( 8UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define ADC_CHANNEL_3_SMP   (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define ADC_CHANNEL_4_SMP   (ADC_SMPR1_REGOFFSET | ((16UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define ADC_CHANNEL_5_SMP   (ADC_SMPR1_REGOFFSET | ((20UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define ADC_AWD_CR1_REGOFFSET   (0x00000000UL)
#define ADC_AWD_CR2_REGOFFSET   (0x00100000UL)
#define ADC_AWD_CR3_REGOFFSET   (0x00200000UL)
#define ADC_AWD_CR12_REGOFFSETGAP_MASK   (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_CR12_REGOFFSETGAP_VAL   (0x00000010UL)
#define ADC_AWD_CRX_REGOFFSET_MASK   (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_CR1_CHANNEL_MASK   (ADC16_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define ADC_AWD_CR23_CHANNEL_MASK   (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK   (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define ADC_AWD_CRX_REGOFFSET_POS   (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define ADC_AWD_TR1_REGOFFSET   (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET   (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET   (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK   (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS   (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define ADC_AWD_TRX_BIT_HIGH_MASK   (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define ADC_AWD_TRX_BIT_HIGH_POS   (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define ADC_AWD_TRX_BIT_HIGH_SHIFT4   (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define ADC_OFFSET0_REGOFFSET   (0x00000000UL)
#define ADC_OFFSET1_REGOFFSET   (0x00000001UL)
#define ADC_OFFSET2_REGOFFSET   (0x00000002UL)
#define ADC_OFFSET3_REGOFFSET   (0x00000003UL)
#define ADC_OFFSET4_REGOFFSET   (0x00000004UL)
#define ADC_OFFSET5_REGOFFSET   (0x00000005UL)
#define ADC_OFFSETx_REGOFFSET_MASK
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS   (ADC_CFGR_AWD1SGL_Pos)
#define ADC_CFGR_AWD1EN_BITOFFSET_POS   (ADC_CFGR_AWD1EN_Pos)
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS   (ADC_CFGR_JAWD1EN_Pos)
#define ADC_TR1_HT1_BITOFFSET_POS   (ADC_TR1_HT1_Pos)
#define ADC_CR_BITS_PROPERTY_RS   (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define DDL_ADC16_REG_TRIG_SOFTWARE   (0x00000000UL)
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC1   (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC2   (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC3   (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR2_CC2   (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR3_TRGO   (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR4_CC4   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_EINT_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR1_TRGO   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR2_TRGO   (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR4_TRGO   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_TMR3_CC4   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_LPTMROUT   (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_REG_TRIG_EXT_RISING   ( ADC_CFGR_EXTEN_0)
#define DDL_ADC16_REG_TRIG_EXT_FALLING   (ADC_CFGR_EXTEN_1 )
#define DDL_ADC16_REG_TRIG_EXT_RISINGFALLING   (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
#define DDL_ADC16_REG_SEQ_SCAN_DISABLE   (0x00000000UL)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS   ( ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS   ( ADC_SQR1_RL_1 )
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS   ( ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS   ( ADC_SQR1_RL_2 )
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 )
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS   ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS   (ADC_SQR1_RL_3 )
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 )
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS   (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)
#define DDL_ADC16_REG_SEQ_DISCONT_DISABLE   (0x00000000UL)
#define DDL_ADC16_REG_SEQ_DISCONT_1RANK   ( ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_SEQ_DISCONT_2RANKS   ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_SEQ_DISCONT_3RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_SEQ_DISCONT_4RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define DDL_ADC16_REG_RANK_1   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_2   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_3   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_4   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_5   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_6   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_7   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_8   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_9   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_10   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_11   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define DDL_ADC16_REG_RANK_12   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define DDL_ADC16_INJ_SEQ_SCAN_DISABLE   (0x00000000UL)
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_2RANKS   ( ADC_JSQR_JL_0)
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_3RANKS   (ADC_JSQR_JL_1 )
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_4RANKS   (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define DDL_ADC16_INJ_SEQ_DISCONT_DISABLE   (0x00000000UL)
#define DDL_ADC16_INJ_SEQ_DISCONT_1RANK   (ADC_CFGR_JDISCEN)
#define DDL_ADC16_MULTI_INDEPENDENT   (0x00000000UL)
#define DDL_ADC16_MULTI_DUAL_REG_SIMULT   (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_1)
#define DDL_ADC16_MULTI_DUAL_REG_INTERL   (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_1 | ADC_CR_DUALMOD_0)
#define DDL_ADC16_MULTI_DUAL_INJ_SIMULT   (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_0)
#define DDL_ADC16_MULTI_DUAL_INJ_ALTERN   (ADC_CR_DUALMOD_3 | ADC_CR_DUALMOD_0)
#define DDL_ADC16_MULTI_DUAL_REG_SIM_INJ_SIM   (ADC_CR_DUALMOD_0)
#define DDL_ADC16_MULTI_DUAL_REG_SIM_INJ_ALT   (ADC_CR_DUALMOD_1)
#define DDL_ADC16_MULTI_DUAL_REG_INT_INJ_SIM   (ADC_CR_DUALMOD_1 | ADC_CR_DUALMOD_0)
#define DDL_ADC16_CR_ADDIS_NOT_EXECUTED   (0x00000000UL)
#define DDL_ADC16_CR_ADDIS_EXECUTION_IN_PROGRESS   ADC_CR_ADDIS
#define DDL_ADC16_SINGLE_INP0   (0x00U)
#define DDL_ADC16_SINGLE_INP1   (0x01U)
#define DDL_ADC16_SINGLE_INP2   (0x02U)
#define DDL_ADC16_SINGLE_INN0   (0x03U)
#define DDL_ADC16_SINGLE_INN1   (0x04U)
#define DDL_ADC16_SINGLE_INN2   (0x05U)
#define DDL_ADC16_DIFF_CHANNEL0   (0x00U)
#define DDL_ADC16_DIFF_CHANNEL1   (0x01U)
#define DDL_ADC16_DIFF_CHANNEL2   (0x02U)
#define DDL_ADC16_DMA_REG_REGULAR_DATA   (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by DDL function @ref DDL_ADC16_REG_ReadConversionData32() and other functions @ref DDL_ADC16_REG_ReadConversionDatax() */
#define DDL_ADC16_LP_MODE_NONE   (0x00000000UL)
#define DDL_ADC16_LP_AUTOWAIT   (ADC_CFGR_AUTDLY)
#define DDL_ADC16_OFFSET_0   ADC_OFFSET0_REGOFFSET
#define DDL_ADC16_OFFSET_1   ADC_OFFSET1_REGOFFSET
#define DDL_ADC16_OFFSET_2   ADC_OFFSET2_REGOFFSET
#define DDL_ADC16_OFFSET_3   ADC_OFFSET3_REGOFFSET
#define DDL_ADC16_OFFSET_4   ADC_OFFSET4_REGOFFSET
#define DDL_ADC16_OFFSET_5   ADC_OFFSET5_REGOFFSET
#define DDL_ADC16_OFFSET_DISABLE   (0x00000000UL)
#define DDL_ADC16_OFFSET_ENABLE   (ADC_OFFSET1_OFFSET1_EN)
#define DDL_ADC16_OFFSET_SIGN_NEGATIVE   (0x00000000UL)
#define DDL_ADC16_OFFSET_SIGN_POSITIVE   (ADC_OFFSET1_OFFSETPOS)
#define DDL_ADC16_CHANNEL_0   (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
#define DDL_ADC16_CHANNEL_1   (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
#define DDL_ADC16_CHANNEL_2   (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
#define DDL_ADC16_CHANNEL_3   (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
#define DDL_ADC16_CHANNEL_4   (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
#define DDL_ADC16_CHANNEL_5   (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
#define DDL_ADC16_REG_CONV_SINGLE   (0x00000000UL)
#define DDL_ADC16_REG_CONV_CONTINUOUS   (ADC_CFGR_CONT)
#define DDL_ADC16_REG_DMA_TRANSFER_NONE   (0x00000000UL)
#define DDL_ADC16_REG_DMA_TRANSFER_LIMITED   ( ADC_CFGR_DMAEN)
#define DDL_ADC16_REG_DMA_TRANSFER_UNLIMITED   (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
#define DDL_ADC16_REG_OVR_DATA_PRESERVED   (0x00000000UL)
#define DDL_ADC16_REG_OVR_DATA_OVERWRITTEN   (ADC_CFGR_OVRMOD)
#define DDL_ADC16_INJ_TRIG_SOFTWARE   (0x00000000UL)
#define DDL_ADC16_INJ_TRIG_EXT_TMR1_TRGO   (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR1_CC4   (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_TRGO   (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_CC1   (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_CC4   (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR4_TRGO   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_EINT_LINE15   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_CC3   (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_TRGO   (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_CC1   (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_LPTMROUT   (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define DDL_ADC16_INJ_TRIG_EXT_RISING   ( ADC_JSQR_JEXTEN_0)
#define DDL_ADC16_INJ_TRIG_EXT_FALLING   (ADC_JSQR_JEXTEN_1 )
#define DDL_ADC16_INJ_TRIG_EXT_RISINGFALLING   (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
#define DDL_ADC16_INJ_RANK_1   (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define DDL_ADC16_INJ_RANK_2   (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define DDL_ADC16_INJ_RANK_3   (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define DDL_ADC16_INJ_RANK_4   (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define DDL_ADC16_INJ_TRIG_INDEPENDENT   (0x00000000UL)
#define DDL_ADC16_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)
#define DDL_ADC16_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE   (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define DDL_ADC16_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define DDL_ADC16_INJ_QUEUE_DISABLE   (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
#define DDL_ADC16_SAMPLINGTIME_1CYCLES   (0x00000000)
#define DDL_ADC16_SAMPLINGTIME_2CYCLES   (ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_3CYCLES   (ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_4CYCLES   (ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_5CYCLES   (ADC_SMPR1_SMP0_2)
#define DDL_ADC16_SAMPLINGTIME_6CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_7CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_8CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_9CYCLES   (ADC_SMPR1_SMP0_3)
#define DDL_ADC16_SAMPLINGTIME_10CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_11CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_12CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_13CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2)
#define DDL_ADC16_SAMPLINGTIME_14CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_15CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_16CYCLES   (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_AWD1   (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define DDL_ADC16_AWD2   (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
#define DDL_ADC16_AWD3   (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
#define DDL_ADC16_AWD_DISABLE   (0x00000000UL)
#define DDL_ADC16_AWD_ALL_CHANNELS_REG   (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
#define DDL_ADC16_AWD_ALL_CHANNELS_INJ   (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
#define DDL_ADC16_AWD_ALL_CHANNELS_REG_INJ   (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
#define DDL_ADC16_AWD_CHANNEL_0_REG   ((DDL_ADC16_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_0_INJ   ((DDL_ADC16_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_0_REG_INJ   ((DDL_ADC16_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_1_REG   ((DDL_ADC16_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_1_INJ   ((DDL_ADC16_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_1_REG_INJ   ((DDL_ADC16_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_2_REG   ((DDL_ADC16_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_2_INJ   ((DDL_ADC16_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_2_REG_INJ   ((DDL_ADC16_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_3_REG   ((DDL_ADC16_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_3_INJ   ((DDL_ADC16_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_3_REG_INJ   ((DDL_ADC16_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_4_REG   ((DDL_ADC16_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_4_INJ   ((DDL_ADC16_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_4_REG_INJ   ((DDL_ADC16_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_5_REG   ((DDL_ADC16_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_5_INJ   ((DDL_ADC16_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_CHANNEL_5_REG_INJ   ((DDL_ADC16_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define DDL_ADC16_AWD_THRESHOLD_HIGH   (ADC_TR1_HT1 )
#define DDL_ADC16_AWD_THRESHOLD_LOW   ( ADC_TR1_LT1)
#define DDL_ADC16_AWD_THRESHOLDS_HIGH_LOW   (ADC_TR1_HT1 | ADC_TR1_LT1)
#define DDL_ADC16_OVS_DISABLE   (0x00000000UL)
#define DDL_ADC16_OVS_GRP_REGULAR_CONTINUED   ( ADC_CFGR2_ROVSE)
#define DDL_ADC16_OVS_GRP_REGULAR_RESUMED   (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
#define DDL_ADC16_OVS_GRP_INJECTED   ( ADC_CFGR2_JOVSE )
#define DDL_ADC16_OVS_GRP_INJ_REG_RESUMED   ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
#define DDL_ADC16_OVS_REG_CONT   (0x00000000UL)
#define DDL_ADC16_OVS_REG_DISCONT   (ADC_CFGR2_TROVS)
#define DDL_ADC16_OVS_RATIO_2   (0x00000000UL)
#define DDL_ADC16_OVS_RATIO_4   ( ADC_CFGR2_OVSR_0)
#define DDL_ADC16_OVS_RATIO_8   ( ADC_CFGR2_OVSR_1 )
#define DDL_ADC16_OVS_RATIO_16   ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
#define DDL_ADC16_OVS_SHIFT_NONE   (0x00000000UL)
#define DDL_ADC16_OVS_SHIFT_RIGHT_1   ( ADC_CFGR2_OVSS_0)
#define DDL_ADC16_OVS_SHIFT_RIGHT_2   ( ADC_CFGR2_OVSS_1 )
#define DDL_ADC16_OVS_SHIFT_RIGHT_3   ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
#define DDL_ADC16_OVS_SHIFT_RIGHT_4   ( ADC_CFGR2_OVSS_2 )
#define DDL_ADC16_FLAG_EOC   ADC_ISR_EOC
#define DDL_ADC16_FLAG_EOS   ADC_ISR_EOS
#define DDL_ADC16_FLAG_OVR   ADC_ISR_OVR
#define DDL_ADC16_FLAG_EOSMP   ADC_ISR_EOSMP
#define DDL_ADC16_FLAG_JEOC   ADC_ISR_JEOC
#define DDL_ADC16_FLAG_JEOS   ADC_ISR_JEOS
#define DDL_ADC16_FLAG_JQOVF   ADC_ISR_JQOVF
#define DDL_ADC16_FLAG_AWD1   ADC_ISR_AWD1
#define DDL_ADC16_FLAG_AWD2   ADC_ISR_AWD2
#define DDL_ADC16_FLAG_AWD3   ADC_ISR_AWD3
#define DDL_ADC16_IT_EOC   ADC_IER_EOCIE
#define DDL_ADC16_IT_EOS   ADC_IER_EOSIE
#define DDL_ADC16_IT_OVR   ADC_IER_OVRIE
#define DDL_ADC16_IT_EOSMP   ADC_IER_EOSMPIE
#define DDL_ADC16_IT_JEOC   ADC_IER_JEOCIE
#define DDL_ADC16_IT_JEOS   ADC_IER_JEOSIE
#define DDL_ADC16_IT_JQOVF   ADC_IER_JQOVFIE
#define DDL_ADC16_IT_AWD1   ADC_IER_AWD1IE
#define DDL_ADC16_IT_AWD2   ADC_IER_AWD2IE
#define DDL_ADC16_IT_AWD3   ADC_IER_AWD3IE
#define DDL_ADC16_SINGLE_ENDED   (0x00000000)
#define DDL_ADC16_DIFFERENTIAL_ENDED   (ADC_CFGR2_DIFSEL_Msk)
#define DDL_ADC16_AWD_FILTERING_NONE   (0x00000000UL)
#define DDL_ADC16_AWD_FILTERING_2SAMPLES   ( ADC_CFGR2_AWDFILT_0)
#define DDL_ADC16_AWD_FILTERING_3SAMPLES   ( ADC_CFGR2_AWDFILT_1 )
#define DDL_ADC16_AWD_FILTERING_4SAMPLES   ( ADC_CFGR2_AWDFILT_1 | ADC_CFGR2_AWDFILT_0)
#define DDL_ADC16_AWD_FILTERING_5SAMPLES   (ADC_CFGR2_AWDFILT_2 )
#define DDL_ADC16_AWD_FILTERING_6SAMPLES   (ADC_CFGR2_AWDFILT_2 | ADC_CFGR2_AWDFILT_0)
#define DDL_ADC16_AWD_FILTERING_7SAMPLES   (ADC_CFGR2_AWDFILT_2 | ADC_CFGR2_AWDFILT_1 )
#define DDL_ADC16_AWD_FILTERING_8SAMPLES   (ADC_CFGR2_AWDFILT_2 | ADC_CFGR2_AWDFILT_1 | ADC_CFGR2_AWDFILT_0)
#define DDL_ADC16_VREF_INTERNAL   (ADC_CAL_REF_SEL)
#define DDL_ADC16_VREF_EXTERNAL   (0x00000000)
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)
 Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define __DDL_ADC16_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
 Helper macro to get ADC channel number in decimal format from literals DDL_ADC16_CHANNEL_x.

Functions

__STATIC_INLINE uint32_t DDL_ADC16_DMA_GetRegAddr (ADC16_TypeDef *ADCx, uint32_t Register)
 Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void DDL_ADC16_SetLowPowerMode (ADC16_TypeDef *ADCx, uint32_t LowPowerMode)
 Set ADC low power mode.
__STATIC_INLINE uint32_t DDL_ADC16_GetLowPowerMode (ADC16_TypeDef *ADCx)
 Get ADC low power mode:
__STATIC_INLINE void DDL_ADC16_SetOffset (ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
 Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetLevel (ADC16_TypeDef *ADCx, uint32_t Offsety)
 Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void DDL_ADC16_SetOffsetState (ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
 Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetState (ADC16_TypeDef *ADCx, uint32_t Offsety)
 Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void DDL_ADC16_SetOffsetSign (ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
 Set for the ADC selected offset number 1, 2, 3 or 4: choose offset sign.
__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetSign (ADC16_TypeDef *ADCx, uint32_t Offsety)
 Get for the ADC selected offset number 1, 2, 3 or 4: offset sign if positive or negative.
__STATIC_INLINE void DDL_ADC16_REG_SetTriggerSource (ADC16_TypeDef *ADCx, uint32_t TriggerSource)
 Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetTriggerSource (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t DDL_ADC16_REG_IsTriggerSourceSWStart (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void DDL_ADC16_REG_SetTriggerEdge (ADC16_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
 Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetTriggerEdge (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void DDL_ADC16_REG_SetSequencerLength (ADC16_TypeDef *ADCx, uint32_t SequencerNbRanks)
 Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerLength (ADC16_TypeDef *ADCx)
 Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void DDL_ADC16_REG_SetSequencerDiscont (ADC16_TypeDef *ADCx, uint32_t SeqDiscont)
 Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerDiscont (ADC16_TypeDef *ADCx)
 Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void DDL_ADC16_REG_SetSequencerRanks (ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
 Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerRanks (ADC16_TypeDef *ADCx, uint32_t Rank)
 Get ADC group regular sequence: channel on the selected scan sequence rank. Refer to description of function DDL_ADC16_REG_SetSequencerLength().
__STATIC_INLINE void DDL_ADC16_REG_SetContinuousMode (ADC16_TypeDef *ADCx, uint32_t Continuous)
 Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetContinuousMode (ADC16_TypeDef *ADCx)
 Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void DDL_ADC16_REG_SetDMATransfer (ADC16_TypeDef *ADCx, uint32_t DMATransfer)
 Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetDMATransfer (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void DDL_ADC16_REG_SetOverrun (ADC16_TypeDef *ADCx, uint32_t Overrun)
 Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t DDL_ADC16_REG_GetOverrun (ADC16_TypeDef *ADCx)
 Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void DDL_ADC16_INJ_SetTriggerSource (ADC16_TypeDef *ADCx, uint32_t TriggerSource)
 Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTriggerSource (ADC16_TypeDef *ADCx)
 Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsTriggerSourceSWStart (ADC16_TypeDef *ADCx)
 Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void DDL_ADC16_INJ_SetTriggerEdge (ADC16_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
 Set ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTriggerEdge (ADC16_TypeDef *ADCx)
 Get ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger.
__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerLength (ADC16_TypeDef *ADCx, uint32_t SequencerNbRanks)
 Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerLength (ADC16_TypeDef *ADCx)
 Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerDiscont (ADC16_TypeDef *ADCx, uint32_t SeqDiscont)
 Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerDiscont (ADC16_TypeDef *ADCx)
 Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerRanks (ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
 Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerRanks (ADC16_TypeDef *ADCx, uint32_t Rank)
 Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void DDL_ADC16_INJ_SetTrigAuto (ADC16_TypeDef *ADCx, uint32_t TrigAuto)
 Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTrigAuto (ADC16_TypeDef *ADCx)
 Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void DDL_ADC16_INJ_SetQueueMode (ADC16_TypeDef *ADCx, uint32_t QueueMode)
 Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetQueueMode (ADC16_TypeDef *ADCx)
 Get ADC group injected context queue mode.
__STATIC_INLINE void DDL_ADC16_INJ_ConfigQueueContext (ADC16_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
 Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime (ADC16_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
 Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t DDL_ADC16_GetChannelSamplingTime (ADC16_TypeDef *ADCx, uint32_t Channel)
 Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void DDL_ADC16_SetDisableCommand (ADC16_TypeDef *ADCx)
 Set ADC Disable Command.
__STATIC_INLINE uint32_t DDL_ADC16_GetDisableCommandStatus (ADC16_TypeDef *ADCx)
 Get ADC Disable Command.
__STATIC_INLINE void DDL_ADC16_SetChannelSingleDiff (ADC16_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
 Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t DDL_ADC16_GetChannelSingleDiff (ADC16_TypeDef *ADCx, uint32_t Channel)
 Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void DDL_ADC16_SetAnalogWDMonitChannels (ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
 Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t DDL_ADC16_GetAnalogWDMonitChannels (ADC16_TypeDef *ADCx, uint32_t AWDy)
 Get ADC analog watchdog monitored channel.
__STATIC_INLINE void DDL_ADC16_ConfigAnalogWDThresholds (ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
 Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void DDL_ADC16_SetAnalogWDThresholds (ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
 Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t DDL_ADC16_GetAnalogWDThresholds (ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
 Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void DDL_ADC16_SetAWDFilteringConfiguration (ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
 Set ADC analog watchdog filtering configuration.
__STATIC_INLINE uint32_t DDL_ADC16_GetAWDFilteringConfiguration (ADC16_TypeDef *ADCx, uint32_t AWDy)
 Get ADC analog watchdog filtering configuration.
__STATIC_INLINE void DDL_ADC16_SetOverSamplingScope (ADC16_TypeDef *ADCx, uint32_t OvsScope)
 Set ADC oversampling scope: ADC groups regular and-or injected.
__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingScope (ADC16_TypeDef *ADCx)
 Get ADC oversampling scope: ADC groups regular and-or injected.
__STATIC_INLINE void DDL_ADC16_SetOverSamplingDiscont (ADC16_TypeDef *ADCx, uint32_t OverSamplingDiscont)
 Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingDiscont (ADC16_TypeDef *ADCx)
 Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void DDL_ADC16_ConfigOverSamplingRatioShift (ADC16_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
 Set ADC oversampling (impacting both ADC groups regular and injected).
__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingRatio (ADC16_TypeDef *ADCx)
 Get ADC oversampling ratio (impacting both ADC groups regular and injected).
__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingShift (ADC16_TypeDef *ADCx)
 Get ADC oversampling shift (impacting both ADC groups regular and injected).
__STATIC_INLINE void DDL_ADC16_SetMultimode (ADC16_TypeDef *ADCx, uint32_t Multimode)
 Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t DDL_ADC16_GetMultimode (ADC16_TypeDef *ADCx)
 Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void DDL_ADC16_Enable (ADC16_TypeDef *ADCx)
 Enable the selected ADC instance.
__STATIC_INLINE void DDL_ADC16_Disable (ADC16_TypeDef *ADCx)
 Disable the selected ADC instance.
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabled (ADC16_TypeDef *ADCx)
 Get the selected ADC instance enable state.
__STATIC_INLINE void DDL_ADC16_REG_StartConversion (ADC16_TypeDef *ADCx)
 Start ADC group regular conversion.
__STATIC_INLINE void DDL_ADC16_REG_StopConversion (ADC16_TypeDef *ADCx)
 Stop ADC group regular conversion.
__STATIC_INLINE uint32_t DDL_ADC16_REG_IsConversionOngoing (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion state.
__STATIC_INLINE uint32_t DDL_ADC16_REG_IsStopConversionOngoing (ADC16_TypeDef *ADCx)
 Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t DDL_ADC16_REG_ReadConversionData32 (ADC16_TypeDef *ADCx)
 Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE void DDL_ADC16_INJ_StartConversion (ADC16_TypeDef *ADCx)
 Start ADC group injected conversion.
__STATIC_INLINE void DDL_ADC16_INJ_StopConversion (ADC16_TypeDef *ADCx)
 Stop ADC group injected conversion.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsConversionOngoing (ADC16_TypeDef *ADCx)
 Get ADC group injected conversion state.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsStopConversionOngoing (ADC16_TypeDef *ADCx)
 Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t DDL_ADC16_INJ_ReadConversionData32 (ADC16_TypeDef *ADCx, uint32_t Rank)
 Get ADC group injected conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE void DDL_ADC16_SetVerfInternal (ADC16_TypeDef *ADCx)
 Set VREF to be internally generated.
__STATIC_INLINE void DDL_ADC16_SetVerfExternal (ADC16_TypeDef *ADCx)
 Determine whether the current setting of VREF is internally generated or externally connected.
__STATIC_INLINE uint32_t DDL_ADC16_GetVerfStatus (ADC16_TypeDef *ADCx)
 Get VREF Status.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOC (ADC16_TypeDef *ADCx)
 Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOS (ADC16_TypeDef *ADCx)
 Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_OVR (ADC16_TypeDef *ADCx)
 Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOSMP (ADC16_TypeDef *ADCx)
 Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JEOC (ADC16_TypeDef *ADCx)
 Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JEOS (ADC16_TypeDef *ADCx)
 Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JQOVF (ADC16_TypeDef *ADCx)
 Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD1 (ADC16_TypeDef *ADCx)
 Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD2 (ADC16_TypeDef *ADCx)
 Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD3 (ADC16_TypeDef *ADCx)
 Get flag ADC analog watchdog 3.
__STATIC_INLINE void DDL_ADC16_ClearFlag_EOC (ADC16_TypeDef *ADCx)
 Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_ClearFlag_EOS (ADC16_TypeDef *ADCx)
 Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_ClearFlag_OVR (ADC16_TypeDef *ADCx)
 Clear flag ADC group regular overrun.
__STATIC_INLINE void DDL_ADC16_ClearFlag_EOSMP (ADC16_TypeDef *ADCx)
 Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void DDL_ADC16_ClearFlag_JEOC (ADC16_TypeDef *ADCx)
 Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_ClearFlag_JEOS (ADC16_TypeDef *ADCx)
 Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_ClearFlag_JQOVF (ADC16_TypeDef *ADCx)
 Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD1 (ADC16_TypeDef *ADCx)
 Clear flag ADC analog watchdog 1.
__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD2 (ADC16_TypeDef *ADCx)
 Clear flag ADC analog watchdog 2.
__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD3 (ADC16_TypeDef *ADCx)
 Clear flag ADC analog watchdog 3.
__STATIC_INLINE void DDL_ADC16_EnableIT_EOC (ADC16_TypeDef *ADCx)
 Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_EnableIT_EOS (ADC16_TypeDef *ADCx)
 Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_EnableIT_OVR (ADC16_TypeDef *ADCx)
 Enable ADC group regular interruption overrun.
__STATIC_INLINE void DDL_ADC16_EnableIT_EOSMP (ADC16_TypeDef *ADCx)
 Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void DDL_ADC16_EnableIT_JEOC (ADC16_TypeDef *ADCx)
 Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_EnableIT_JEOS (ADC16_TypeDef *ADCx)
 Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_EnableIT_JQOVF (ADC16_TypeDef *ADCx)
 Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void DDL_ADC16_EnableIT_AWD1 (ADC16_TypeDef *ADCx)
 Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void DDL_ADC16_EnableIT_AWD2 (ADC16_TypeDef *ADCx)
 Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void DDL_ADC16_EnableIT_AWD3 (ADC16_TypeDef *ADCx)
 Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void DDL_ADC16_DisableIT_EOC (ADC16_TypeDef *ADCx)
 Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_DisableIT_EOS (ADC16_TypeDef *ADCx)
 Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_DisableIT_OVR (ADC16_TypeDef *ADCx)
 Disable interruption ADC group regular overrun.
__STATIC_INLINE void DDL_ADC16_DisableIT_EOSMP (ADC16_TypeDef *ADCx)
 Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void DDL_ADC16_DisableIT_JEOC (ADC16_TypeDef *ADCx)
 Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void DDL_ADC16_DisableIT_JEOS (ADC16_TypeDef *ADCx)
 Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void DDL_ADC16_DisableIT_JQOVF (ADC16_TypeDef *ADCx)
 Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void DDL_ADC16_DisableIT_AWD1 (ADC16_TypeDef *ADCx)
 Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void DDL_ADC16_DisableIT_AWD2 (ADC16_TypeDef *ADCx)
 Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void DDL_ADC16_DisableIT_AWD3 (ADC16_TypeDef *ADCx)
 Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOC (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOS (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_OVR (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOSMP (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JEOC (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JEOS (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JQOVF (ADC16_TypeDef *ADCx)
 Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD1 (ADC16_TypeDef *ADCx)
 Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD2 (ADC16_TypeDef *ADCx)
 Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD3 (ADC16_TypeDef *ADCx)
 Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime_Single (ADC16_TypeDef *ADCx, uint32_t SingleCh, uint32_t SamplingTime)
 Set the sampling time for a single-ended ADC channel. The sampling time is in terms of ADC clock cycles.
__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime_Diff (ADC16_TypeDef *ADCx, uint32_t DiffCh, uint32_t SamplingTime)
 Set the sampling time for a differential ADC channel. The function updates both the positive and negative input channel.
__STATIC_INLINE void DDL_ADC16_SetSequencerRanks_Single (ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t SingleCh)
 Configure a single-ended channel rank in the regular conversion sequence.
__STATIC_INLINE void DDL_ADC16_SetSequencerRanks_Diff (ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t DiffCh)
 Configure a differential channel rank in the regular conversion sequence.
ErrorStatus DDL_ADC16_DeInit (ADC16_TypeDef *ADCx)
 De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus DDL_ADC16_Init (ADC16_TypeDef *ADCx, DDL_ADC16_InitTypeDef *ADC_InitStruct)
 Initialize some features of ADC instance.
void DDL_ADC16_StructInit (DDL_ADC16_InitTypeDef *ADC_InitStruct)
 Set each DDL_ADC16_InitTypeDef field to default value.
ErrorStatus DDL_ADC16_REG_Init (ADC16_TypeDef *ADCx, DDL_ADC16_REG_InitTypeDef *ADC_REG_InitStruct)
 Initialize some features of ADC group regular.
void DDL_ADC16_REG_StructInit (DDL_ADC16_REG_InitTypeDef *ADC_REG_InitStruct)
 Set each DDL_ADC16_REG_InitTypeDef field to default value.
ErrorStatus DDL_ADC16_INJ_Init (ADC16_TypeDef *ADCx, DDL_ADC16_INJ_InitTypeDef *ADC_INJ_InitStruct)
 Initialize some features of ADC group injected.
void DDL_ADC16_INJ_StructInit (DDL_ADC16_INJ_InitTypeDef *ADC_INJ_InitStruct)
 Set each DDL_ADC16_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC DDL module.

Attention

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The original code has been modified by Geehy Semiconductor.

Copyright (c) 2017 STMicroelectronics. Copyright (C) 2025 Geehy Semiconductor. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file g32r4xx_ddl_adc16.h.

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