g32r4xx_ddl_adc16.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_ADC16_H
#define G32R4xx_DDL_ADC16_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined (ADC1) || defined (ADC2)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
 
/* Private constants ---------------------------------------------------------*/
 
/* Internal mask for ADC group regular sequencer:                             */
/* To select into literal DDL_ADC16_REG_RANK_x the relevant bits for:            */
/* - sequencer register offset                                                */
/* - sequencer rank bits position into the selected register                  */
 
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SQR1_REGOFFSET                              (0x00000000UL)
#define ADC_SQR2_REGOFFSET                              (0x00000100UL)
 
#define ADC_REG_SQRX_REGOFFSET_MASK                     (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS                          (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK                       (0x1F)
 
/* Definition of ADC group regular sequencer bits information to be inserted  */
/* into ADC group regular sequencer ranks literals definition.                */
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ1_Pos)
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ2_Pos)
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ3_Pos)
#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ4_Pos)
#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ5_Pos)
#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ6_Pos)
#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS               (ADC_SQR1_SQ7_Pos)
#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS               (ADC_SQR2_SQ8_Pos)
#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS               (ADC_SQR2_SQ9_Pos)
#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS              (ADC_SQR2_SQ10_Pos)
#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS              (ADC_SQR2_SQ11_Pos)
#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS              (ADC_SQR2_SQ12_Pos)
 
/* Internal mask for ADC group injected sequencer:                            */
/* To select into literal DDL_ADC16_INJ_RANK_x the relevant bits for:            */
/* - data register offset                                                     */
/* - sequencer rank bits position into the selected register                  */
 
/* Internal register offset for ADC group injected data register */
/* (offset placed into a spare area of literal definition) */
#define ADC_JDR1_REGOFFSET                              (0x00000000UL)
#define ADC_JDR2_REGOFFSET                              (0x00000100UL)
#define ADC_JDR3_REGOFFSET                              (0x00000200UL)
#define ADC_JDR4_REGOFFSET                              (0x00000300UL)
 
#define ADC_INJ_JDRX_REGOFFSET_MASK                     (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
                                            | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK                       (0x1F)
#define ADC_JDRX_REGOFFSET_POS                          (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
 
/* Definition of ADC group injected sequencer bits information to be inserted */
/* into ADC group injected sequencer ranks literals definition.               */
#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS               (ADC_JSQR_JSQ1_Pos)
#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS               (ADC_JSQR_JSQ2_Pos)
#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS               (ADC_JSQR_JSQ3_Pos)
#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS               (ADC_JSQR_JSQ4_Pos)
 
/* Internal mask for ADC group regular trigger:                               */
/* To select into literal DDL_ADC16_REG_TRIG_x the relevant bits for:            */
/* - regular trigger source                                                   */
/* - regular trigger edge                                                     */
#define ADC_REG_TRIG_EXT_EDGE_DEFAULT                   (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */
 
/* Mask containing trigger source masks for each of possible                  */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC_REG_TRIG_SOURCE_MASK                        (((DDL_ADC16_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_CFGR_EXTSEL)                             << (4U * 3UL))  )
 
/* Mask containing trigger edge masks for each of possible                    */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC_REG_TRIG_EDGE_MASK                          (((DDL_ADC16_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
 
/* Definition of ADC group regular trigger bits information.                  */
#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS               (ADC_CFGR_EXTSEL_Pos)
#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS                (ADC_CFGR_EXTEN_Pos)
 
/* Internal mask for ADC group injected trigger:                              */
/* To select into literal DDL_ADC16_INJ_TRIG_x the relevant bits for:            */
/* - injected trigger source                                                  */
/* - injected trigger edge                                                    */
#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT                   (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */
 
/* Mask containing trigger source masks for each of possible                  */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC_INJ_TRIG_SOURCE_MASK                        (((DDL_ADC16_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
 
/* Mask containing trigger edge masks for each of possible                    */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
#define ADC_INJ_TRIG_EDGE_MASK                          (((DDL_ADC16_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
 
/* Definition of ADC group injected trigger bits information.                 */
#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS               (ADC_JSQR_JEXTSEL_Pos)
#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS                (ADC_JSQR_JEXTEN_Pos)
 
/* Internal mask for ADC channel:                                             */
/* To select into literal DDL_ADC16_CHANNEL_x the relevant bits for:             */
/* - channel identifier defined by number                                     */
/* - channel identifier defined by bitfield                                   */
/* - channel differentiation between external channels (connected to          */
/*   GPIO pins) and internal channels (connected to internal paths)           */
/* - channel sampling time defined by SMPRx register offset                   */
/*   and SMPx bits positions into SMPRx register                              */
#define ADC16_CFGR_AWD1CH                               (0x7UL << ADC_CFGR_AWD1CH_Pos)
#define ADC_CHANNEL_ID_NUMBER_MASK                      (ADC16_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK                    (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS             (ADC_CFGR_AWD1CH_Pos)
#define ADC_CHANNEL_ID_MASK                             (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
                                            | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0              (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
 
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH                      (0x80000000UL) /* Marker of internal channel */
#define ADC_CHANNEL_ID_INTERNAL_CH_2                    (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define ADC_CHANNEL_ID_INTERNAL_CH_MASK                 (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
 
/* Internal register offset for ADC channel sampling time configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SMPR1_REGOFFSET                             (0x00000000UL)
#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK                (ADC_SMPR1_REGOFFSET)
#define ADC_SMPRX_REGOFFSET_POS                         (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
 
#define ADC_CHANNEL_SMPx_BITOFFSET_MASK                 (0x01F00000UL)
#define ADC_CHANNEL_SMPx_BITOFFSET_POS                  (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
 
/* Definition of channels ID number information to be inserted into           */
/* channels literals definition.                                              */
#define ADC_CHANNEL_0_NUMBER                            (0x00000000UL)
#define ADC_CHANNEL_1_NUMBER                            (ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_2_NUMBER                            (ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_3_NUMBER                            (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_4_NUMBER                            (ADC_CFGR_AWD1CH_2)
#define ADC_CHANNEL_5_NUMBER                            (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
 
/* Definition of channels ID bitfield information to be inserted into         */
/* channels literals definition.                                              */
#define ADC_CHANNEL_0_BITFIELD                          (ADC_AWD2CR_AWD2CH_0)
#define ADC_CHANNEL_1_BITFIELD                          (ADC_AWD2CR_AWD2CH_1)
#define ADC_CHANNEL_2_BITFIELD                          (ADC_AWD2CR_AWD2CH_2)
#define ADC_CHANNEL_3_BITFIELD                          (ADC_AWD2CR_AWD2CH_3)
#define ADC_CHANNEL_4_BITFIELD                          (ADC_AWD2CR_AWD2CH_4)
#define ADC_CHANNEL_5_BITFIELD                          (ADC_AWD2CR_AWD2CH_5)
 
/* Definition of channels sampling time information to be inserted into       */
/* channels literals definition.                                              */
#define ADC_CHANNEL_0_SMP                               (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define ADC_CHANNEL_1_SMP                               (ADC_SMPR1_REGOFFSET | (( 4UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define ADC_CHANNEL_2_SMP                               (ADC_SMPR1_REGOFFSET | (( 8UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define ADC_CHANNEL_3_SMP                               (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define ADC_CHANNEL_4_SMP                               (ADC_SMPR1_REGOFFSET | ((16UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define ADC_CHANNEL_5_SMP                               (ADC_SMPR1_REGOFFSET | ((20UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
 
/* Internal mask for ADC analog watchdog:                                     */
/* To select into literals DDL_ADC16_AWD_CHANNELx_xxx the relevant bits for:     */
/* (concatenation of multiple bits used in different analog watchdogs,        */
/* - analog watchdog 1: monitored channel defined by number,                  */
/*   selection of ADC group (ADC groups regular and-or injected).             */
/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
/*   selection on groups.                                                     */
 
/* Internal register offset for ADC analog watchdog channel configuration */
#define ADC_AWD_CR1_REGOFFSET                           (0x00000000UL)
#define ADC_AWD_CR2_REGOFFSET                           (0x00100000UL)
#define ADC_AWD_CR3_REGOFFSET                           (0x00200000UL)
 
/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
#define ADC_AWD_CR12_REGOFFSETGAP_MASK                  (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_CR12_REGOFFSETGAP_VAL                   (0x00000010UL)
 
#define ADC_AWD_CRX_REGOFFSET_MASK                      (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
 
#define ADC_AWD_CR1_CHANNEL_MASK                        (ADC16_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define ADC_AWD_CR23_CHANNEL_MASK                       (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK                     (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
 
#define ADC_AWD_CRX_REGOFFSET_POS                       (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
 
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC_AWD_TR1_REGOFFSET                           (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET                           (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET                           (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK                      (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS                       (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define ADC_AWD_TRX_BIT_HIGH_MASK                       (0x00010000UL)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define ADC_AWD_TRX_BIT_HIGH_POS                        (16UL)                           /* Selection of 1 bit to discriminate threshold high: position of bit */
#define ADC_AWD_TRX_BIT_HIGH_SHIFT4                     (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
 
/* Internal mask for ADC offset:                                              */
/* Internal register offset for ADC offset number configuration */
#define ADC_OFFSET0_REGOFFSET                           (0x00000000UL)
#define ADC_OFFSET1_REGOFFSET                           (0x00000001UL)
#define ADC_OFFSET2_REGOFFSET                           (0x00000002UL)
#define ADC_OFFSET3_REGOFFSET                           (0x00000003UL)
#define ADC_OFFSET4_REGOFFSET                           (0x00000004UL)
#define ADC_OFFSET5_REGOFFSET                           (0x00000005UL)
#define ADC_OFFSETx_REGOFFSET_MASK                      (ADC_OFFSET0_REGOFFSET | ADC_OFFSET1_REGOFFSET \
                                          | ADC_OFFSET2_REGOFFSET | ADC_OFFSET3_REGOFFSET \
                                          | ADC_OFFSET4_REGOFFSET | ADC_OFFSET5_REGOFFSET)
 
/* ADC registers bits positions */
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS                  (ADC_CFGR_AWD1SGL_Pos)
#define ADC_CFGR_AWD1EN_BITOFFSET_POS                   (ADC_CFGR_AWD1EN_Pos)
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS                  (ADC_CFGR_JAWD1EN_Pos)
#define ADC_TR1_HT1_BITOFFSET_POS                       (ADC_TR1_HT1_Pos)
 
/* ADC registers bits groups */
#define ADC_CR_BITS_PROPERTY_RS                         (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

 
#define DDL_ADC16_REG_TRIG_SOFTWARE         (0x00000000UL)                                                                               
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC1     (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                              
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC2     (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          
#define DDL_ADC16_REG_TRIG_EXT_TMR1_CC3     (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          
#define DDL_ADC16_REG_TRIG_EXT_TMR2_CC2     (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC16_REG_TRIG_EXT_TMR3_TRGO    (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          
#define DDL_ADC16_REG_TRIG_EXT_TMR4_CC4     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC16_REG_TRIG_EXT_EINT_LINE11  (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC16_REG_TRIG_EXT_TMR1_TRGO    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC16_REG_TRIG_EXT_TMR2_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                          
#define DDL_ADC16_REG_TRIG_EXT_TMR4_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC16_REG_TRIG_EXT_TMR3_CC4     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      
#define DDL_ADC16_REG_TRIG_EXT_LPTMROUT     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  

#define DDL_ADC16_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)  
#define DDL_ADC16_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )  
#define DDL_ADC16_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)  

#define DDL_ADC16_REG_SEQ_SCAN_DISABLE         (0x00000000UL)                                                  
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS   (                                             ADC_SQR1_RL_0)    
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS   (                              ADC_SQR1_RL_1               )    
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS   (                              ADC_SQR1_RL_1 | ADC_SQR1_RL_0)   
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS   (               ADC_SQR1_RL_2                              )    
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS   (               ADC_SQR1_RL_2                | ADC_SQR1_RL_0)   
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS   (               ADC_SQR1_RL_2 | ADC_SQR1_RL_1               )   
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS   (               ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)  
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS   (ADC_SQR1_RL_3                                             )    
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS  (ADC_SQR1_RL_3                               | ADC_SQR1_RL_0)   
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS  (ADC_SQR1_RL_3                | ADC_SQR1_RL_1               )   
#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS  (ADC_SQR1_RL_3                | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)  

#define DDL_ADC16_REG_SEQ_DISCONT_DISABLE  (0x00000000UL)                                                                    
#define DDL_ADC16_REG_SEQ_DISCONT_1RANK    (                                                               ADC_CFGR_DISCEN)  
#define DDL_ADC16_REG_SEQ_DISCONT_2RANKS   (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  
#define DDL_ADC16_REG_SEQ_DISCONT_3RANKS   (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN)  
#define DDL_ADC16_REG_SEQ_DISCONT_4RANKS   (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  
#define DDL_ADC16_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN)  
#define DDL_ADC16_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  

#define DDL_ADC16_REG_RANK_1   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_2   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_3   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_4   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_5   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_6   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_7   (ADC_SQR1_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_8   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_9   (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)   
#define DDL_ADC16_REG_RANK_10  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)  
#define DDL_ADC16_REG_RANK_11  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)  
#define DDL_ADC16_REG_RANK_12  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)  

#define DDL_ADC16_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                   
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0)  
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                )  
#define DDL_ADC16_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)  

#define DDL_ADC16_INJ_SEQ_DISCONT_DISABLE  (0x00000000UL)      
#define DDL_ADC16_INJ_SEQ_DISCONT_1RANK    (ADC_CFGR_JDISCEN)  

#define DDL_ADC16_MULTI_INDEPENDENT           (0x00000000UL)                                            
#define DDL_ADC16_MULTI_DUAL_REG_SIMULT       (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_1)                     
#define DDL_ADC16_MULTI_DUAL_REG_INTERL       (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_1 | ADC_CR_DUALMOD_0)  
#define DDL_ADC16_MULTI_DUAL_INJ_SIMULT       (ADC_CR_DUALMOD_2 | ADC_CR_DUALMOD_0)                     
#define DDL_ADC16_MULTI_DUAL_INJ_ALTERN       (ADC_CR_DUALMOD_3 | ADC_CR_DUALMOD_0)                     
#define DDL_ADC16_MULTI_DUAL_REG_SIM_INJ_SIM  (ADC_CR_DUALMOD_0)                                        
#define DDL_ADC16_MULTI_DUAL_REG_SIM_INJ_ALT  (ADC_CR_DUALMOD_1)                                        
#define DDL_ADC16_MULTI_DUAL_REG_INT_INJ_SIM  (ADC_CR_DUALMOD_1 | ADC_CR_DUALMOD_0)                     

#define DDL_ADC16_CR_ADDIS_NOT_EXECUTED           (0x00000000UL)
#define DDL_ADC16_CR_ADDIS_EXECUTION_IN_PROGRESS  ADC_CR_ADDIS

#define DDL_ADC16_SINGLE_INP0  (0x00U)  
#define DDL_ADC16_SINGLE_INP1  (0x01U)  
#define DDL_ADC16_SINGLE_INP2  (0x02U)  
#define DDL_ADC16_SINGLE_INN0  (0x03U)  
#define DDL_ADC16_SINGLE_INN1  (0x04U)  
#define DDL_ADC16_SINGLE_INN2  (0x05U)  

#define DDL_ADC16_DIFF_CHANNEL0  (0x00U)  
#define DDL_ADC16_DIFF_CHANNEL1  (0x01U)  
#define DDL_ADC16_DIFF_CHANNEL2  (0x02U)  

 
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)

typedef struct
{
  uint32_t LowPowerMode;  
 
} DDL_ADC16_InitTypeDef;

typedef struct
{
  uint32_t TriggerSource;     
 
  uint32_t SequencerLength;   
 
  uint32_t SequencerDiscont;  
 
  uint32_t ContinuousMode;    
 
  uint32_t DMATransfer;       
 
  uint32_t Overrun;           
 
} DDL_ADC16_REG_InitTypeDef;

typedef struct
{
  uint32_t TriggerSource;     
 
  uint32_t SequencerLength;   
 
  uint32_t SequencerDiscont;  
 
  uint32_t TrigAuto;          
 
} DDL_ADC16_INJ_InitTypeDef;

#endif /* USE_FULL_DDL_DRIVER */
 
/* Private macros ------------------------------------------------------------*/
/* List of ADC registers intended to be used (most commonly) with             */
/* DMA transfer.                                                              */
/* Refer to function @ref DDL_ADC16_DMA_GetRegAddr().                            */
#define DDL_ADC16_DMA_REG_REGULAR_DATA  (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by DDL function @ref DDL_ADC16_REG_ReadConversionData32() and other functions @ref DDL_ADC16_REG_ReadConversionDatax() */

#define DDL_ADC16_LP_MODE_NONE  (0x00000000UL)     
#define DDL_ADC16_LP_AUTOWAIT   (ADC_CFGR_AUTDLY)  

#define DDL_ADC16_OFFSET_0  ADC_OFFSET0_REGOFFSET  
#define DDL_ADC16_OFFSET_1  ADC_OFFSET1_REGOFFSET  
#define DDL_ADC16_OFFSET_2  ADC_OFFSET2_REGOFFSET  
#define DDL_ADC16_OFFSET_3  ADC_OFFSET3_REGOFFSET  
#define DDL_ADC16_OFFSET_4  ADC_OFFSET4_REGOFFSET  
#define DDL_ADC16_OFFSET_5  ADC_OFFSET5_REGOFFSET  

#define DDL_ADC16_OFFSET_DISABLE  (0x00000000UL)            
#define DDL_ADC16_OFFSET_ENABLE   (ADC_OFFSET1_OFFSET1_EN)  

#define DDL_ADC16_OFFSET_SIGN_NEGATIVE  (0x00000000UL)           
#define DDL_ADC16_OFFSET_SIGN_POSITIVE  (ADC_OFFSET1_OFFSETPOS)  

#define DDL_ADC16_CHANNEL_0  (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD )  
#define DDL_ADC16_CHANNEL_1  (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD )  
#define DDL_ADC16_CHANNEL_2  (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD )  
#define DDL_ADC16_CHANNEL_3  (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD )  
#define DDL_ADC16_CHANNEL_4  (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD )  
#define DDL_ADC16_CHANNEL_5  (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD )  

#define DDL_ADC16_REG_CONV_SINGLE      (0x00000000UL)   
#define DDL_ADC16_REG_CONV_CONTINUOUS  (ADC_CFGR_CONT)  

#define DDL_ADC16_REG_DMA_TRANSFER_NONE       (0x00000000UL)                      
#define DDL_ADC16_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)  
#define DDL_ADC16_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)  

#define DDL_ADC16_REG_OVR_DATA_PRESERVED    (0x00000000UL)     
#define DDL_ADC16_REG_OVR_DATA_OVERWRITTEN  (ADC_CFGR_OVRMOD)  

#define DDL_ADC16_INJ_TRIG_SOFTWARE         (0x00000000UL)                                                                                  
#define DDL_ADC16_INJ_TRIG_EXT_TMR1_TRGO    (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                 
#define DDL_ADC16_INJ_TRIG_EXT_TMR1_CC4     (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                            
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_TRGO    (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                            
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_CC1     (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC16_INJ_TRIG_EXT_TMR2_CC4     (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                            
#define DDL_ADC16_INJ_TRIG_EXT_TMR4_TRGO    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC16_INJ_TRIG_EXT_EINT_LINE15  (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_CC3     (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)  
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_TRGO    (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                            
#define DDL_ADC16_INJ_TRIG_EXT_TMR3_CC1     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       
#define DDL_ADC16_INJ_TRIG_EXT_LPTMROUT     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       

#define DDL_ADC16_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0)  
#define DDL_ADC16_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    )  
#define DDL_ADC16_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)  

#define DDL_ADC16_INJ_RANK_1  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)  
#define DDL_ADC16_INJ_RANK_2  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)  
#define DDL_ADC16_INJ_RANK_3  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)  
#define DDL_ADC16_INJ_RANK_4  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)  

#define DDL_ADC16_INJ_TRIG_INDEPENDENT       (0x00000000UL)    
#define DDL_ADC16_INJ_TRIG_FROM_GRP_REGULAR  (ADC_CFGR_JAUTO)  

#define DDL_ADC16_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE  (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define DDL_ADC16_INJ_QUEUE_2CONTEXTS_END_EMPTY    (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define DDL_ADC16_INJ_QUEUE_DISABLE                (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

#define DDL_ADC16_SAMPLINGTIME_1CYCLES   (0x00000000)
#define DDL_ADC16_SAMPLINGTIME_2CYCLES   (ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_3CYCLES   (ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_4CYCLES   (ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_5CYCLES   (ADC_SMPR1_SMP0_2)
#define DDL_ADC16_SAMPLINGTIME_6CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_7CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_8CYCLES   (ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_9CYCLES   (ADC_SMPR1_SMP0_3)
#define DDL_ADC16_SAMPLINGTIME_10CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_11CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_12CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_13CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2)
#define DDL_ADC16_SAMPLINGTIME_14CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_0)
#define DDL_ADC16_SAMPLINGTIME_15CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1)
#define DDL_ADC16_SAMPLINGTIME_16CYCLES  (ADC_SMPR1_SMP0_3 | ADC_SMPR1_SMP0_2 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_0)


#define DDL_ADC16_AWD1  (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET)  
#define DDL_ADC16_AWD2  (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)  
#define DDL_ADC16_AWD3  (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)  

#define DDL_ADC16_AWD_DISABLE               (0x00000000UL)                                                                                          
#define DDL_ADC16_AWD_ALL_CHANNELS_REG      (ADC_AWD_CR23_CHANNEL_MASK                                     | ADC_CFGR_AWD1EN                   )    
#define DDL_ADC16_AWD_ALL_CHANNELS_INJ      (ADC_AWD_CR23_CHANNEL_MASK                  | ADC_CFGR_JAWD1EN                                     )    
#define DDL_ADC16_AWD_ALL_CHANNELS_REG_INJ  (ADC_AWD_CR23_CHANNEL_MASK                  | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   )    
#define DDL_ADC16_AWD_CHANNEL_0_REG         ((DDL_ADC16_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_0_INJ         ((DDL_ADC16_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_0_REG_INJ     ((DDL_ADC16_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_1_REG         ((DDL_ADC16_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_1_INJ         ((DDL_ADC16_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_1_REG_INJ     ((DDL_ADC16_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_2_REG         ((DDL_ADC16_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_2_INJ         ((DDL_ADC16_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_2_REG_INJ     ((DDL_ADC16_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_3_REG         ((DDL_ADC16_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_3_INJ         ((DDL_ADC16_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_3_REG_INJ     ((DDL_ADC16_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_4_REG         ((DDL_ADC16_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_4_INJ         ((DDL_ADC16_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_4_REG_INJ     ((DDL_ADC16_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_5_REG         ((DDL_ADC16_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_5_INJ         ((DDL_ADC16_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL)  
#define DDL_ADC16_AWD_CHANNEL_5_REG_INJ     ((DDL_ADC16_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  


#define DDL_ADC16_AWD_THRESHOLD_HIGH       (ADC_TR1_HT1              )  
#define DDL_ADC16_AWD_THRESHOLD_LOW        (              ADC_TR1_LT1)  
#define DDL_ADC16_AWD_THRESHOLDS_HIGH_LOW  (ADC_TR1_HT1 | ADC_TR1_LT1)  

#define DDL_ADC16_OVS_DISABLE                (0x00000000UL)                                         
#define DDL_ADC16_OVS_GRP_REGULAR_CONTINUED  (                                    ADC_CFGR2_ROVSE)  
#define DDL_ADC16_OVS_GRP_REGULAR_RESUMED    (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE)  
#define DDL_ADC16_OVS_GRP_INJECTED           (                  ADC_CFGR2_JOVSE                  )  
#define DDL_ADC16_OVS_GRP_INJ_REG_RESUMED    (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)  

#define DDL_ADC16_OVS_REG_CONT     (0x00000000UL)     
#define DDL_ADC16_OVS_REG_DISCONT  (ADC_CFGR2_TROVS)  

#define DDL_ADC16_OVS_RATIO_2   (0x00000000UL)                                            
#define DDL_ADC16_OVS_RATIO_4   (                                      ADC_CFGR2_OVSR_0)  
#define DDL_ADC16_OVS_RATIO_8   (                   ADC_CFGR2_OVSR_1                   )  
#define DDL_ADC16_OVS_RATIO_16  (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)  

#define DDL_ADC16_OVS_SHIFT_NONE     (0x00000000UL)                                                               
#define DDL_ADC16_OVS_SHIFT_RIGHT_1  (                                                         ADC_CFGR2_OVSS_0)  
#define DDL_ADC16_OVS_SHIFT_RIGHT_2  (                                      ADC_CFGR2_OVSS_1                   )  
#define DDL_ADC16_OVS_SHIFT_RIGHT_3  (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)  
#define DDL_ADC16_OVS_SHIFT_RIGHT_4  (                   ADC_CFGR2_OVSS_2                                      )  

#define DDL_ADC16_FLAG_EOC    ADC_ISR_EOC    
#define DDL_ADC16_FLAG_EOS    ADC_ISR_EOS    
#define DDL_ADC16_FLAG_OVR    ADC_ISR_OVR    
#define DDL_ADC16_FLAG_EOSMP  ADC_ISR_EOSMP  
#define DDL_ADC16_FLAG_JEOC   ADC_ISR_JEOC   
#define DDL_ADC16_FLAG_JEOS   ADC_ISR_JEOS   
#define DDL_ADC16_FLAG_JQOVF  ADC_ISR_JQOVF  
#define DDL_ADC16_FLAG_AWD1   ADC_ISR_AWD1   
#define DDL_ADC16_FLAG_AWD2   ADC_ISR_AWD2   
#define DDL_ADC16_FLAG_AWD3   ADC_ISR_AWD3   

#define DDL_ADC16_IT_EOC    ADC_IER_EOCIE    
#define DDL_ADC16_IT_EOS    ADC_IER_EOSIE    
#define DDL_ADC16_IT_OVR    ADC_IER_OVRIE    
#define DDL_ADC16_IT_EOSMP  ADC_IER_EOSMPIE  
#define DDL_ADC16_IT_JEOC   ADC_IER_JEOCIE   
#define DDL_ADC16_IT_JEOS   ADC_IER_JEOSIE   
#define DDL_ADC16_IT_JQOVF  ADC_IER_JQOVFIE  
#define DDL_ADC16_IT_AWD1   ADC_IER_AWD1IE   
#define DDL_ADC16_IT_AWD2   ADC_IER_AWD2IE   
#define DDL_ADC16_IT_AWD3   ADC_IER_AWD3IE   

#define DDL_ADC16_SINGLE_ENDED        (0x00000000)            
#define DDL_ADC16_DIFFERENTIAL_ENDED  (ADC_CFGR2_DIFSEL_Msk)  

#define DDL_ADC16_AWD_FILTERING_NONE      (0x00000000UL)                                                     
#define DDL_ADC16_AWD_FILTERING_2SAMPLES  (                                            ADC_CFGR2_AWDFILT_0)  
#define DDL_ADC16_AWD_FILTERING_3SAMPLES  (                      ADC_CFGR2_AWDFILT_1                      )  
#define DDL_ADC16_AWD_FILTERING_4SAMPLES  (                      ADC_CFGR2_AWDFILT_1 | ADC_CFGR2_AWDFILT_0)  
#define DDL_ADC16_AWD_FILTERING_5SAMPLES  (ADC_CFGR2_AWDFILT_2                                            )  
#define DDL_ADC16_AWD_FILTERING_6SAMPLES  (ADC_CFGR2_AWDFILT_2 |                       ADC_CFGR2_AWDFILT_0)  
#define DDL_ADC16_AWD_FILTERING_7SAMPLES  (ADC_CFGR2_AWDFILT_2 | ADC_CFGR2_AWDFILT_1                      )  
#define DDL_ADC16_AWD_FILTERING_8SAMPLES  (ADC_CFGR2_AWDFILT_2 | ADC_CFGR2_AWDFILT_1 | ADC_CFGR2_AWDFILT_0)  

#define DDL_ADC16_VREF_INTERNAL  (ADC_CAL_REF_SEL)
#define DDL_ADC16_VREF_EXTERNAL  (0x00000000)


 
/* Private macros ------------------------------------------------------------*/

#define __ADC_PTR_REG_OFFSET(__REG__,                   __REG_OFFFSET__)                         \
  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

#define __DDL_ADC16_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)  \
  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
   (                                                                                       \
       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
   )                                                                                       \
   :                                                                                       \
   (                                                                                       \
       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
   )                                                                                       \
  )

 
/* Exported functions --------------------------------------------------------*/
/* Note: DDL ADC functions to set DMA transfer are located into sections of    */
/*       configuration of ADC instance, groups and multimode (if available):  */
/*       @ref DDL_ADC16_REG_SetDMATransfer(), ...                                */

__STATIC_INLINE uint32_t DDL_ADC16_DMA_GetRegAddr(ADC16_TypeDef *ADCx, uint32_t Register)
{
  /* Prevent unused argument(s) compilation warning */
  (void)(Register);
 
  /* Retrieve address of register DR */
  return (uint32_t) &(ADCx->DR);
}



__STATIC_INLINE void DDL_ADC16_SetLowPowerMode(ADC16_TypeDef *ADCx, uint32_t LowPowerMode)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetLowPowerMode(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
}

__STATIC_INLINE void DDL_ADC16_SetOffset(ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
{
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  MODIFY_REG(*preg,
             ADC_OFFSET1_OFFSET1_EN | ADC_OFFSET1_OFFSET1,
             ADC_OFFSET1_OFFSET1_EN | OffsetLevel);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetLevel(ADC16_TypeDef *ADCx, uint32_t Offsety)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  return (uint32_t) READ_BIT(*preg, ADC_OFFSET1_OFFSET1);
}

__STATIC_INLINE void DDL_ADC16_SetOffsetState(ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  MODIFY_REG(*preg,
             ADC_OFFSET1_OFFSET1_EN,
             OffsetState);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetState(ADC16_TypeDef *ADCx, uint32_t Offsety)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  return (uint32_t) READ_BIT(*preg, ADC_OFFSET1_OFFSET1_EN);
}

__STATIC_INLINE void DDL_ADC16_SetOffsetSign(ADC16_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  MODIFY_REG(*preg,
             ADC_OFFSET1_OFFSETPOS,
             OffsetSign);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOffsetSign(ADC16_TypeDef *ADCx, uint32_t Offsety)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFFSET0, Offsety);
 
  return (uint32_t) READ_BIT(*preg, ADC_OFFSET1_OFFSETPOS);
}


__STATIC_INLINE void DDL_ADC16_REG_SetTriggerSource(ADC16_TypeDef *ADCx, uint32_t TriggerSource)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetTriggerSource(ADC16_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_IsTriggerSourceSWStart(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (DDL_ADC16_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC16_REG_SetTriggerEdge(ADC16_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetTriggerEdge(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
}

__STATIC_INLINE void DDL_ADC16_REG_SetSequencerLength(ADC16_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  MODIFY_REG(ADCx->SQR1, ADC_SQR1_RL, SequencerNbRanks);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerLength(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_RL));
}

__STATIC_INLINE void DDL_ADC16_REG_SetSequencerDiscont(ADC16_TypeDef *ADCx, uint32_t SeqDiscont)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerDiscont(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
}

__STATIC_INLINE void DDL_ADC16_REG_SetSequencerRanks(ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register and register position depending on parameter "Rank".         */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
  __IO uint32_t value = ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
  __IO uint32_t temp = 0;
  uint32_t regVal;
 
  switch(value)
  {
    case 0: temp = 1; break;
    case 1: temp = 2; break;
    case 2: temp = 3; break;
    case 3: temp = 4; break;
    case 4: temp = 8; break;
    case 5: temp = 12; break;
    default: temp = 0; break;
  }
 
     regVal = *preg;
 
     regVal &= ~(ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
 
     regVal |= (temp << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
 
     *preg = regVal;
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetSequencerRanks(ADC16_TypeDef *ADCx, uint32_t Rank)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
  __IO uint32_t value = (READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK));
  __IO uint32_t temp = 0;
 
  switch(value)
  {
    case 1: temp = 0; break;
    case 2: temp = 1; break;
    case 3: temp = 2; break;
    case 4: temp = 3; break;
    case 8: temp = 4; break;
    case 12: temp = 5; break;
  }
 
  return (uint32_t)(temp << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
}

__STATIC_INLINE void DDL_ADC16_REG_SetContinuousMode(ADC16_TypeDef *ADCx, uint32_t Continuous)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetContinuousMode(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
}

__STATIC_INLINE void DDL_ADC16_REG_SetDMATransfer(ADC16_TypeDef *ADCx, uint32_t DMATransfer)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetDMATransfer(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
}

__STATIC_INLINE void DDL_ADC16_REG_SetOverrun(ADC16_TypeDef *ADCx, uint32_t Overrun)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_GetOverrun(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
}


__STATIC_INLINE void DDL_ADC16_INJ_SetTriggerSource(ADC16_TypeDef *ADCx, uint32_t TriggerSource)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTriggerSource(ADC16_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsTriggerSourceSWStart(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (DDL_ADC16_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC16_INJ_SetTriggerEdge(ADC16_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTriggerEdge(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}

__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerLength(ADC16_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerLength(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}

__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerDiscont(ADC16_TypeDef *ADCx, uint32_t SeqDiscont)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerDiscont(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
}

__STATIC_INLINE void DDL_ADC16_INJ_SetSequencerRanks(ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register depending on parameter "Rank".                               */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  __IO uint32_t value = ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
  __IO uint32_t temp = 0;
 
  switch(value)
  {
    case 0: temp = 1; break;
    case 1: temp = 2; break;
    case 2: temp = 3; break;
    case 3: temp = 4; break;
    case 4: temp = 8; break;
    case 5: temp = 12; break;
    default: temp = 0; break;
  }
 
  MODIFY_REG(ADCx->JSQR,
             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
             temp << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetSequencerRanks(ADC16_TypeDef *ADCx, uint32_t Rank)
{
  __IO uint32_t value = (READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
  __IO uint32_t temp = 0;
  switch(value)
  {
    case 1: temp = 0; break;
    case 2: temp = 1; break;
    case 3: temp = 2; break;
    case 4: temp = 3; break;
    case 8: temp = 4; break;
    case 12: temp = 5; break;
  }
 
  return (uint32_t)(temp << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS);
}

__STATIC_INLINE void DDL_ADC16_INJ_SetTrigAuto(ADC16_TypeDef *ADCx, uint32_t TrigAuto)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetTrigAuto(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
}

__STATIC_INLINE void DDL_ADC16_INJ_SetQueueMode(ADC16_TypeDef *ADCx, uint32_t QueueMode)
{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_GetQueueMode(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
}

__STATIC_INLINE void DDL_ADC16_INJ_ConfigQueueContext(ADC16_TypeDef *ADCx,
                                                   uint32_t TriggerSource,
                                                   uint32_t ExternalTriggerEdge,
                                                   uint32_t SequencerNbRanks,
                                                   uint32_t Rank1_Channel,
                                                   uint32_t Rank2_Channel,
                                                   uint32_t Rank3_Channel,
                                                   uint32_t Rank4_Channel)
{
  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
  /* in register depending on literal "DDL_ADC16_INJ_RANK_x".                    */
  /* Parameters "Rankx_Channel" and "DDL_ADC16_INJ_RANK_x" are used with masks   */
  /* because containing other bits reserved for other purpose.                */
  /* If parameter "TriggerSource" is set to SW start, then parameter          */
  /* "ExternalTriggerEdge" is discarded.                                      */
  uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != DDL_ADC16_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
  MODIFY_REG(ADCx->JSQR,
             ADC_JSQR_JEXTSEL |
             ADC_JSQR_JEXTEN  |
             ADC_JSQR_JSQ4    |
             ADC_JSQR_JSQ3    |
             ADC_JSQR_JSQ2    |
             ADC_JSQR_JSQ1    |
             ADC_JSQR_JL,
             (TriggerSource & ADC_JSQR_JEXTSEL)          |
             (ExternalTriggerEdge * (is_trigger_not_sw)) |
             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC16_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC16_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC16_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (DDL_ADC16_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             SequencerNbRanks
            );
}


__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime(ADC16_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
  /* Set bits with content of parameter "SamplingTime" with bits position     */
  /* in register and register position depending on parameter "Channel".      */
  /* Parameter "Channel" is used with masks because containing                */
  /* other bits reserved for other purpose.                                   */
 
  MODIFY_REG(ADCx->SMPR1,
             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}

__STATIC_INLINE uint32_t DDL_ADC16_GetChannelSamplingTime(ADC16_TypeDef *ADCx, uint32_t Channel)
{
  return (uint32_t)(READ_BIT(ADCx->SMPR1,
                             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
                    >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
                   );
}

__STATIC_INLINE void DDL_ADC16_SetDisableCommand(ADC16_TypeDef *ADCx)
{
  MODIFY_REG(ADCx->CR, ADC_CR_ADDIS, DDL_ADC16_CR_ADDIS_EXECUTION_IN_PROGRESS);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetDisableCommandStatus(ADC16_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_ADDIS);
}

__STATIC_INLINE void DDL_ADC16_SetChannelSingleDiff(ADC16_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
  /* Bits for single or differential mode selection for each channel are set  */
  /* to 1 only when the differential mode is selected, and to 0 when the      */
  /* single mode is selected.                                                 */
  (void)Channel;
  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_DIFSEL, SingleDiff);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetChannelSingleDiff(ADC16_TypeDef *ADCx, uint32_t Channel)
{
  (void)Channel;
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_DIFSEL));
}


__STATIC_INLINE void DDL_ADC16_SetAnalogWDMonitChannels(ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
  /* in register and register position depending on parameter "AWDy".         */
  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
 
  MODIFY_REG(*preg,
             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
             AWDChannelGroup & AWDy);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetAnalogWDMonitChannels(ADC16_TypeDef *ADCx, uint32_t AWDy)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
                                                   + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
 
  uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
 
  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
  /* (parameter value DDL_ADC16_AWD_DISABLE).                                    */
  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
  /* or a single channel.                                                     */
  if (AnalogWDMonitChannels != 0UL)
  {
    if (AWDy == DDL_ADC16_AWD1)
    {
      if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
      {
        /* AWD monitoring a group of channels */
        AnalogWDMonitChannels = ((AnalogWDMonitChannels
                                  | (ADC_AWD_CR23_CHANNEL_MASK)
                                 )
                                 & (~(ADC16_CFGR_AWD1CH))
                                );
      }
      else
      {
        /* AWD monitoring a single channel */
        AnalogWDMonitChannels = (AnalogWDMonitChannels
                                 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
                                );
      }
    }
    else
    {
      if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
      {
        /* AWD monitoring a group of channels */
        AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
                                 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
                                );
      }
      else
      {
        /* AWD monitoring a single channel */
        /* AWD monitoring a group of channels */
        AnalogWDMonitChannels = (AnalogWDMonitChannels
                                 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
                                 | (__DDL_ADC16_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
                                );
      }
    }
  }
 
  return AnalogWDMonitChannels;
}

__STATIC_INLINE void DDL_ADC16_ConfigAnalogWDThresholds(ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
                                                     uint32_t AWDThresholdLowValue)
{
  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
  /* position in register and register position depending on parameter        */
  /* "AWDy".                                                                  */
  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
  MODIFY_REG(*preg,
             ADC_TR1_HT1 | ADC_TR1_LT1,
             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
}

__STATIC_INLINE void DDL_ADC16_SetAnalogWDThresholds(ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
                                                  uint32_t AWDThresholdValue)
{
  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
  /* position in register and register position depending on parameters       */
  /* "AWDThresholdsHighLow" and "AWDy".                                       */
  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
  /* containing other bits reserved for other purpose.                        */
  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
                                             ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
  MODIFY_REG(*preg,
             AWDThresholdsHighLow,
             AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
}

__STATIC_INLINE uint32_t DDL_ADC16_GetAnalogWDThresholds(ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
                                                   ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
  return (uint32_t)(READ_BIT(*preg,
                             (AWDThresholdsHighLow | ADC_TR1_LT1))
                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
                        & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
}

__STATIC_INLINE void DDL_ADC16_SetAWDFilteringConfiguration(ADC16_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
{
  /* Prevent unused argument(s) compilation warning */
  (void)(AWDy);
  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_AWDFILT, FilteringConfig);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetAWDFilteringConfiguration(ADC16_TypeDef *ADCx, uint32_t AWDy)
{
  /* Prevent unused argument(s) compilation warning */
  (void)(AWDy);
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_AWDFILT));
}


__STATIC_INLINE void DDL_ADC16_SetOverSamplingScope(ADC16_TypeDef *ADCx, uint32_t OvsScope)
{
  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingScope(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
}

__STATIC_INLINE void DDL_ADC16_SetOverSamplingDiscont(ADC16_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingDiscont(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
}

__STATIC_INLINE void DDL_ADC16_ConfigOverSamplingRatioShift(ADC16_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
{
  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingRatio(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
}

__STATIC_INLINE uint32_t DDL_ADC16_GetOverSamplingShift(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
}


__STATIC_INLINE void DDL_ADC16_SetMultimode(ADC16_TypeDef *ADCx, uint32_t Multimode)
{
  MODIFY_REG(ADCx->CR, ADC_CR_DUALMOD, Multimode);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetMultimode(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_DUALMOD));
}


__STATIC_INLINE void DDL_ADC16_Enable(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADEN,
             ADC_CR_ADEN);
}

__STATIC_INLINE void DDL_ADC16_Disable(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADEN,
             0);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabled(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_ADC16_REG_StartConversion(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADSTART,
             ADC_CR_ADSTART);
}

__STATIC_INLINE void DDL_ADC16_REG_StopConversion(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_ADSTP,
             ADC_CR_ADSTP);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_IsConversionOngoing(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_IsStopConversionOngoing(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_REG_ReadConversionData32(ADC16_TypeDef *ADCx)
{
  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA | ADC_DR_ADC2RDATA));
}



__STATIC_INLINE void DDL_ADC16_INJ_StartConversion(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_JADSTART,
             ADC_CR_JADSTART);
}

__STATIC_INLINE void DDL_ADC16_INJ_StopConversion(ADC16_TypeDef *ADCx)
{
  /* Note: Write register with some additional bits forced to state reset     */
  /*       instead of modifying only the selected bit for this function,      */
  /*       to not interfere with bits with HW property "rs".                  */
  MODIFY_REG(ADCx->CR,
             ADC_CR_JADSTP,
             ADC_CR_JADSTP);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsConversionOngoing(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_IsStopConversionOngoing(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_INJ_ReadConversionData32(ADC16_TypeDef *ADCx, uint32_t Rank)
{
  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
 
  return (uint32_t)(READ_BIT(*preg,ADC_JDR1_JDATA));
}



__STATIC_INLINE void DDL_ADC16_SetVerfInternal(ADC16_TypeDef *ADCx)
{
  MODIFY_REG(ADCx->CAL, ADC_CAL_REF_SEL, DDL_ADC16_VREF_INTERNAL);
}

__STATIC_INLINE void DDL_ADC16_SetVerfExternal(ADC16_TypeDef *ADCx)
{
  MODIFY_REG(ADCx->CAL, ADC_CAL_REF_SEL, DDL_ADC16_VREF_EXTERNAL);
}

__STATIC_INLINE uint32_t DDL_ADC16_GetVerfStatus(ADC16_TypeDef *ADCx)
{
  return (uint32_t)READ_BIT(ADCx->CAL, ADC_CAL_REF_SEL);
}



__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOC(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_EOC) == (DDL_ADC16_FLAG_EOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOS(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_EOS) == (DDL_ADC16_FLAG_EOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_OVR(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_OVR) == (DDL_ADC16_FLAG_OVR)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_EOSMP(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_EOSMP) == (DDL_ADC16_FLAG_EOSMP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JEOC(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_JEOC) == (DDL_ADC16_FLAG_JEOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JEOS(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_JEOS) == (DDL_ADC16_FLAG_JEOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_JQOVF(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_JQOVF) == (DDL_ADC16_FLAG_JQOVF)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD1(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_AWD1) == (DDL_ADC16_FLAG_AWD1)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD2(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_AWD2) == (DDL_ADC16_FLAG_AWD2)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsActiveFlag_AWD3(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->ISR, DDL_ADC16_FLAG_AWD3) == (DDL_ADC16_FLAG_AWD3)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_EOC(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_EOC);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_EOS(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_EOS);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_OVR(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_OVR);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_EOSMP(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_EOSMP);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_JEOC(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_JEOC);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_JEOS(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_JEOS);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_JQOVF(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_JQOVF);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD1(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_AWD1);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD2(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_AWD2);
}

__STATIC_INLINE void DDL_ADC16_ClearFlag_AWD3(ADC16_TypeDef *ADCx)
{
  WRITE_REG(ADCx->ISR, DDL_ADC16_FLAG_AWD3);
}



__STATIC_INLINE void DDL_ADC16_EnableIT_EOC(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_EOC);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_EOS(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_EOS);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_OVR(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_OVR);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_EOSMP(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_EOSMP);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_JEOC(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_JEOC);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_JEOS(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_JEOS);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_JQOVF(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_JQOVF);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_AWD1(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_AWD1);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_AWD2(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_AWD2);
}

__STATIC_INLINE void DDL_ADC16_EnableIT_AWD3(ADC16_TypeDef *ADCx)
{
  SET_BIT(ADCx->IER, DDL_ADC16_IT_AWD3);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_EOC(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_EOC);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_EOS(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_EOS);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_OVR(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_OVR);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_EOSMP(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_EOSMP);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_JEOC(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_JEOC);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_JEOS(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_JEOS);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_JQOVF(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_JQOVF);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_AWD1(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_AWD1);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_AWD2(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_AWD2);
}

__STATIC_INLINE void DDL_ADC16_DisableIT_AWD3(ADC16_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->IER, DDL_ADC16_IT_AWD3);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOC(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_EOC) == (DDL_ADC16_IT_EOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOS(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_EOS) == (DDL_ADC16_IT_EOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_OVR(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_OVR) == (DDL_ADC16_IT_OVR)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_EOSMP(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_EOSMP) == (DDL_ADC16_IT_EOSMP)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JEOC(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_JEOC) == (DDL_ADC16_IT_JEOC)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JEOS(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_JEOS) == (DDL_ADC16_IT_JEOS)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_JQOVF(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_JQOVF) == (DDL_ADC16_IT_JQOVF)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD1(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_AWD1) == (DDL_ADC16_IT_AWD1)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD2(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_AWD2) == (DDL_ADC16_IT_AWD2)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_ADC16_IsEnabledIT_AWD3(ADC16_TypeDef *ADCx)
{
  return ((READ_BIT(ADCx->IER, DDL_ADC16_IT_AWD3) == (DDL_ADC16_IT_AWD3)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime_Single(ADC16_TypeDef *ADCx, uint32_t SingleCh, uint32_t SamplingTime)
{
    MODIFY_REG(ADCx->SMPR1,
               (0xFU << (4U * SingleCh)),
               ((SamplingTime & 0xFU) << (4U * SingleCh)));
}

__STATIC_INLINE void DDL_ADC16_SetChannelSamplingTime_Diff(ADC16_TypeDef *ADCx, uint32_t DiffCh, uint32_t SamplingTime)
{
    MODIFY_REG(ADCx->SMPR1,
        (0xFU << (4U * DiffCh)),
        ((SamplingTime & 0xFU) << (4U * DiffCh)));
 
    MODIFY_REG(ADCx->SMPR1,
        (0xFU << (4U * (DiffCh + 3U))),
        ((SamplingTime & 0xFU) << (4U * (DiffCh + 3U))));
}

__STATIC_INLINE void DDL_ADC16_SetSequencerRanks_Single(ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t SingleCh)
{
    uint32_t regVal;
    uint32_t channelMask;
    uint32_t regOffset;
    uint32_t bitOffset;
 
    regOffset = (Rank & 0xFF00U);
    bitOffset = (Rank & 0x00FFU);
 
    channelMask = (0xFU << bitOffset);
 
    if (regOffset == ADC_SQR1_REGOFFSET)
    {
        /* SQR1 register */
        regVal = READ_REG(ADCx->SQR1);
        regVal &= ~channelMask;
 
        if (SingleCh < DDL_ADC16_SINGLE_INN0)
        {
            /* Positive input channel */
            regVal |= ((SingleCh + 1U) << bitOffset);
        }
        else 
        {
            /* Negative input channel */
            /* shifting +2 bits from original position, per original logic. */
            regVal |= ((SingleCh - 2U) << (bitOffset + 2U));
        }
        WRITE_REG(ADCx->SQR1, regVal);
    }
    else if (regOffset == ADC_SQR2_REGOFFSET)
    {
        /* SQR2 register */
        regVal = READ_REG(ADCx->SQR2);
        regVal &= ~channelMask;
 
        if (SingleCh < DDL_ADC16_SINGLE_INN0)
        {
            /* Positive input channel */
            regVal |= ((SingleCh + 1U) << bitOffset);
        }
        else
        {
            /* Negative input channel */
            regVal |= ((SingleCh - 2U) << (bitOffset + 2U));
        }
        WRITE_REG(ADCx->SQR2, regVal);
    }
}

__STATIC_INLINE void DDL_ADC16_SetSequencerRanks_Diff(ADC16_TypeDef *ADCx, uint32_t Rank, uint32_t DiffCh)
{
    uint32_t regVal;
    uint32_t channelMask;
    uint32_t posShifted;
    uint32_t negShifted;
    uint32_t regOffset;
    uint32_t bitOffset;
 
    regOffset = (Rank & 0xFF00U);
    bitOffset = (Rank & 0x00FFU);
    channelMask = (0xFU << bitOffset);
 
    if (regOffset == ADC_SQR1_REGOFFSET)
    {
        /* SQR1 register */
        regVal = READ_REG(ADCx->SQR1);
        regVal &= ~channelMask;
 
        posShifted = ((DiffCh + 1U) << bitOffset);
        negShifted = ((DiffCh + 1U) << (bitOffset + 2U));
        regVal |= (posShifted | negShifted);
 
        WRITE_REG(ADCx->SQR1, regVal);
    }
    else if (regOffset == ADC_SQR2_REGOFFSET)
    {
        /* SQR2 register */
        regVal = READ_REG(ADCx->SQR2);
        regVal &= ~channelMask;
 
        posShifted = ((DiffCh + 1U) << bitOffset);
        negShifted = ((DiffCh + 1U) << (bitOffset + 2U));
        regVal |= (posShifted | negShifted);
 
        WRITE_REG(ADCx->SQR2, regVal);
    }
}

 
#if defined(USE_FULL_DDL_DRIVER)
 
/* De-initialization of ADC instance, ADC group regular and ADC group injected */
/* (availability of ADC group injected depends on G32R4 families) */
ErrorStatus DDL_ADC16_DeInit(ADC16_TypeDef *ADCx);
 
/* Initialization of some features of ADC instance */
ErrorStatus DDL_ADC16_Init(ADC16_TypeDef *ADCx, DDL_ADC16_InitTypeDef *ADC_InitStruct);
void        DDL_ADC16_StructInit(DDL_ADC16_InitTypeDef *ADC_InitStruct);
 
/* Initialization of some features of ADC instance and ADC group regular */
ErrorStatus DDL_ADC16_REG_Init(ADC16_TypeDef *ADCx, DDL_ADC16_REG_InitTypeDef *ADC_REG_InitStruct);
void        DDL_ADC16_REG_StructInit(DDL_ADC16_REG_InitTypeDef *ADC_REG_InitStruct);
 
/* Initialization of some features of ADC instance and ADC group injected */
ErrorStatus DDL_ADC16_INJ_Init(ADC16_TypeDef *ADCx, DDL_ADC16_INJ_InitTypeDef *ADC_INJ_InitStruct);
void        DDL_ADC16_INJ_StructInit(DDL_ADC16_INJ_InitTypeDef *ADC_INJ_InitStruct);

#endif /* USE_FULL_DDL_DRIVER */


 
#endif /* defined (ADC1) || defined (ADC2) */
 
#ifdef __cplusplus
}
#endif
 
#endif