g32r4xx_ddl_dma.c

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#if defined(USE_FULL_DDL_DRIVER)
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx_ddl_dma.h"
#include "g32r4xx_ddl_rcm.h"
#ifdef  USE_FULL_ASSERT
#include "g32_assert.h"
#else
#define ASSERT_PARAM(_PARAM_) ((void)0U)
#endif

 
#if defined (DMA1)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#define IS_DDL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == DDL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == DDL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == DDL_DMA_DIRECTION_MEMORY_TO_MEMORY))
 
#define IS_DDL_DMA_MODE(__VALUE__)               (((__VALUE__) == DDL_DMA_MODE_NORMAL)    || \
                                                 ((__VALUE__) == DDL_DMA_MODE_CIRCULAR)  || \
                                                 ((__VALUE__) == DDL_DMA_MODE_PFCTRL))
 
#define IS_DDL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == DDL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == DDL_DMA_PERIPH_NOINCREMENT))
 
#define IS_DDL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == DDL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == DDL_DMA_MEMORY_NOINCREMENT))
 
#define IS_DDL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == DDL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == DDL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == DDL_DMA_PDATAALIGN_WORD))
 
#define IS_DDL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == DDL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == DDL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == DDL_DMA_MDATAALIGN_WORD))
 
#define IS_DDL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
 
#define IS_DDL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == DDL_DMA_CHANNEL_0)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_1)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_2)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_3)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_4)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_5)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_6)  || \
                                                 ((__VALUE__) == DDL_DMA_CHANNEL_7))
 
#define IS_DDL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == DDL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == DDL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == DDL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == DDL_DMA_PRIORITY_VERYHIGH))
 
#define IS_DDL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
                                                           (((STREAM) == DDL_DMA_STREAM_0) || \
                                                            ((STREAM) == DDL_DMA_STREAM_1) || \
                                                            ((STREAM) == DDL_DMA_STREAM_2) || \
                                                            ((STREAM) == DDL_DMA_STREAM_3) || \
                                                            ((STREAM) == DDL_DMA_STREAM_4) || \
                                                            ((STREAM) == DDL_DMA_STREAM_5) || \
                                                            ((STREAM) == DDL_DMA_STREAM_6) || \
                                                            ((STREAM) == DDL_DMA_STREAM_7) || \
                                                            ((STREAM) == DDL_DMA_STREAM_ALL))))
 
#define IS_DDL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DDL_DMA_FIFOMODE_DISABLE ) || \
                                          ((STATE) == DDL_DMA_FIFOMODE_ENABLE))
 
#define IS_DDL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DDL_DMA_FIFOTHRESHOLD_1_4) || \
                                             ((THRESHOLD) == DDL_DMA_FIFOTHRESHOLD_1_2)  || \
                                             ((THRESHOLD) == DDL_DMA_FIFOTHRESHOLD_3_4)  || \
                                             ((THRESHOLD) == DDL_DMA_FIFOTHRESHOLD_FULL))
 
#define IS_DDL_DMA_MEMORY_BURST(BURST) (((BURST) == DDL_DMA_MBURST_SINGLE) || \
                                       ((BURST) == DDL_DMA_MBURST_INC4)   || \
                                       ((BURST) == DDL_DMA_MBURST_INC8)   || \
                                       ((BURST) == DDL_DMA_MBURST_INC16))
 
#define IS_DDL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DDL_DMA_PBURST_SINGLE) || \
                                           ((BURST) == DDL_DMA_PBURST_INC4)   || \
                                           ((BURST) == DDL_DMA_PBURST_INC8)   || \
                                           ((BURST) == DDL_DMA_PBURST_INC16))

 
/* Private function prototypes -----------------------------------------------*/
 
/* Exported functions --------------------------------------------------------*/


uint32_t DDL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
{
  DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
  ErrorStatus status = SUCCESS;
 
  /* Check the DMA Instance DMAx and Stream parameters*/
  ASSERT_PARAM(IS_DDL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
 
  if (Stream == DDL_DMA_STREAM_ALL)
  {
      DDL_RCM_Unlock();
 
      /* Force reset of DMA clock */
      DDL_RCM_EnableAHBReset(DDL_RCM_AHB_RESET_DMA);
  }
  else
  {
    /* Disable the selected Stream */
    DDL_DMA_DisableStream(DMAx,Stream);
 
    /* Get the DMA Stream Instance */
    tmp = (DMA_Stream_TypeDef *)(__DDL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
 
    /* Reset DMAx_Streamy configuration register */
    DDL_DMA_WriteReg(tmp, SCFG, 0U);
 
    /* Reset DMAx_Streamy remaining bytes register */
    DDL_DMA_WriteReg(tmp, NDATA, 0U);
 
    /* Reset DMAx_Streamy peripheral address register */
    DDL_DMA_WriteReg(tmp, PADDR, 0U);
 
    /* Reset DMAx_Streamy memory address register */
    DDL_DMA_WriteReg(tmp, M0ADDR, 0U);
 
    /* Reset DMAx_Streamy memory address register */
    DDL_DMA_WriteReg(tmp, M1ADDR, 0U);
 
    /* Reset DMAx_Streamy FIFO control register */
    DDL_DMA_WriteReg(tmp, FCTRL, 0x00000021U);
 
    /* Reset Channel register field for DMAx Stream*/
    DDL_DMA_SetChannelSelection(DMAx, Stream, DDL_DMA_CHANNEL_0);
 
    if(Stream == DDL_DMA_STREAM_0)
    {
       /* Reset the Stream0 pending flags */
       DMAx->LIFCLR = 0x0000003FU;
    }
    else if(Stream == DDL_DMA_STREAM_1)
    {
       /* Reset the Stream1 pending flags */
       DMAx->LIFCLR = 0x00000F40U;
    }
    else if(Stream == DDL_DMA_STREAM_2)
    {
       /* Reset the Stream2 pending flags */
       DMAx->LIFCLR = 0x003F0000U;
    }
    else if(Stream == DDL_DMA_STREAM_3)
    {
       /* Reset the Stream3 pending flags */
       DMAx->LIFCLR = 0x0F400000U;
    }
    else if(Stream == DDL_DMA_STREAM_4)
    {
       /* Reset the Stream4 pending flags */
       DMAx->HIFCLR = 0x0000003FU;
    }
    else if(Stream == DDL_DMA_STREAM_5)
    {
       /* Reset the Stream5 pending flags */
       DMAx->HIFCLR = 0x00000F40U;
    }
    else if(Stream == DDL_DMA_STREAM_6)
    {
       /* Reset the Stream6 pending flags */
       DMAx->HIFCLR = 0x003F0000U;
    }
    else if(Stream == DDL_DMA_STREAM_7)
    {
       /* Reset the Stream7 pending flags */
       DMAx->HIFCLR = 0x0F400000U;
    }
    else
    {
      status = ERROR;
    }
  }
 
  return status;
}

uint32_t DDL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, DDL_DMA_InitTypeDef *DMA_InitStruct)
{
  /* Check the DMA Instance DMAx and Stream parameters*/
  ASSERT_PARAM(IS_DDL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
 
  /* Check the DMA parameters from DMA_InitStruct */
  ASSERT_PARAM(IS_DDL_DMA_DIRECTION(DMA_InitStruct->Direction));
  ASSERT_PARAM(IS_DDL_DMA_MODE(DMA_InitStruct->Mode));
  ASSERT_PARAM(IS_DDL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
  ASSERT_PARAM(IS_DDL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
  ASSERT_PARAM(IS_DDL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
  ASSERT_PARAM(IS_DDL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
  ASSERT_PARAM(IS_DDL_DMA_NBDATA(DMA_InitStruct->NbData));
  ASSERT_PARAM(IS_DDL_DMA_CHANNEL(DMA_InitStruct->Channel));
  ASSERT_PARAM(IS_DDL_DMA_PRIORITY(DMA_InitStruct->Priority));
  ASSERT_PARAM(IS_DDL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
     when FIFO mode is enabled */
  if(DMA_InitStruct->FIFOMode != DDL_DMA_FIFOMODE_DISABLE)
  {
    ASSERT_PARAM(IS_DDL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
    ASSERT_PARAM(IS_DDL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
    ASSERT_PARAM(IS_DDL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
  }
 
  /*---------------------------- DMAx SCFGx Configuration ------------------------
   * Configure DMAx_Streamy: data transfer direction, data transfer mode,
   *                          peripheral and memory increment mode,
   *                          data size alignment and  priority level with parameters :
   * - Direction:      DMA_SCFG_DIRCFG[1:0] bits
   * - Mode:           DMA_SCFG_CIRCMEN bit
   * - PeriphOrM2MSrcIncMode:  DMA_SCFG_PERIM bit
   * - MemoryOrM2MDstIncMode:  DMA_SCFG_MEMIM bit
   * - PeriphOrM2MSrcDataSize: DMA_SCFG_PERSIZECFG[1:0] bits
   * - MemoryOrM2MDstDataSize: DMA_SCFG_MEMSIZECFG[1:0] bits
   * - Priority:               DMA_SCFG_PRILCFG[1:0] bits
   */
  DDL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
                        DMA_InitStruct->Mode                    | \
                        DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
                        DMA_InitStruct->MemoryOrM2MDstIncMode   | \
                        DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
                        DMA_InitStruct->MemoryOrM2MDstDataSize  | \
                        DMA_InitStruct->Priority
                        );
 
  if(DMA_InitStruct->FIFOMode != DDL_DMA_FIFOMODE_DISABLE)
  {
    /*---------------------------- DMAx FCTRLx Configuration ------------------------
     * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
     * - FIFOMode:                DMA_FCTRL_DMDEN bit
     * - FIFOThreshold:           DMA_FCTRL_FTHSEL[1:0] bits
     */
    DDL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
 
    /*---------------------------- DMAx SCFGx Configuration --------------------------
     * Configure DMAx_Streamy:  memory burst transfer with parameters :
     * - MemBurst:                DMA_SCFG_MBCFG[1:0] bits
     */
    DDL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
 
    /*---------------------------- DMAx SCFGx Configuration --------------------------
     * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
     * - PeriphBurst:             DMA_SCFG_PBCFG[1:0] bits
     */
    DDL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
  }
 
  /*-------------------------- DMAx M0ADDRx Configuration --------------------------
   * Configure the memory or destination base address with parameter :
   * - MemoryOrM2MDstAddress:     DMA_M0ADDR_M0ADDR[31:0] bits
   */
  DDL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
 
  /*-------------------------- DMAx PADDRx Configuration ---------------------------
   * Configure the peripheral or source base address with parameter :
   * - PeriphOrM2MSrcAddress:     DMA_PADDR_PADDR[31:0] bits
   */
  DDL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
 
  /*--------------------------- DMAx SxNDTR Configuration -------------------------
   * Configure the peripheral base address with parameter :
   * - NbData:                    DMA_NDATA_NDATA[15:0] bits
   */
  DDL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
 
  /*--------------------------- DMA SCFGx_CHSEL Configuration ----------------------
   * Configure the peripheral base address with parameter :
   * - PeriphRequest:             DMA_SCFG_CHSEL[2:0] bits
   */
  DDL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
 
  return SUCCESS;
}

void DDL_DMA_StructInit(DDL_DMA_InitTypeDef *DMA_InitStruct)
{
  /* Set DMA_InitStruct fields to default values */
  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
  DMA_InitStruct->Direction              = DDL_DMA_DIRECTION_PERIPH_TO_MEMORY;
  DMA_InitStruct->Mode                   = DDL_DMA_MODE_NORMAL;
  DMA_InitStruct->PeriphOrM2MSrcIncMode  = DDL_DMA_PERIPH_NOINCREMENT;
  DMA_InitStruct->MemoryOrM2MDstIncMode  = DDL_DMA_MEMORY_NOINCREMENT;
  DMA_InitStruct->PeriphOrM2MSrcDataSize = DDL_DMA_PDATAALIGN_BYTE;
  DMA_InitStruct->MemoryOrM2MDstDataSize = DDL_DMA_MDATAALIGN_BYTE;
  DMA_InitStruct->NbData                 = 0x00000000U;
  DMA_InitStruct->Channel                = DDL_DMA_CHANNEL_0;
  DMA_InitStruct->Priority               = DDL_DMA_PRIORITY_LOW;
  DMA_InitStruct->FIFOMode               = DDL_DMA_FIFOMODE_DISABLE;
  DMA_InitStruct->FIFOThreshold          = DDL_DMA_FIFOTHRESHOLD_1_4;
  DMA_InitStruct->MemBurst               = DDL_DMA_MBURST_SINGLE;
  DMA_InitStruct->PeriphBurst            = DDL_DMA_PBURST_SINGLE;
}



 
#endif /* DMA1 */

 
#endif /* USE_FULL_DDL_DRIVER */