g32r4xx_ddl_dma.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_DMA_H
#define G32R4xx_DDL_DMA_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined (DMA1) || defined (DMA2)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Array used to get the DMA stream register offset versus stream index DDL_DMA_STREAM_x */
static const uint8_t STREAM_OFFSET_TAB[] =
{
  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
};

 
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)
typedef struct
{
  uint32_t PeriphOrM2MSrcAddress;  
 
  uint32_t MemoryOrM2MDstAddress;  
 
  uint32_t Direction;              
 
  uint32_t Mode;                   
 
  uint32_t PeriphOrM2MSrcIncMode;  
 
  uint32_t MemoryOrM2MDstIncMode;  
 
  uint32_t PeriphOrM2MSrcDataSize; 
 
  uint32_t MemoryOrM2MDstDataSize; 
 
  uint32_t NbData;                 
 
  uint32_t Channel;                
 
  uint32_t Priority;               
 
  uint32_t FIFOMode;               
 
  uint32_t FIFOThreshold;          
 
  uint32_t MemBurst;               
 
  uint32_t PeriphBurst;            
 
} DDL_DMA_InitTypeDef;

#endif /*USE_FULL_DDL_DRIVER*/
/* Exported constants --------------------------------------------------------*/

#define DDL_DMA_STREAM_0    0x00000000U
#define DDL_DMA_STREAM_1    0x00000001U
#define DDL_DMA_STREAM_2    0x00000002U
#define DDL_DMA_STREAM_3    0x00000003U
#define DDL_DMA_STREAM_4    0x00000004U
#define DDL_DMA_STREAM_5    0x00000005U
#define DDL_DMA_STREAM_6    0x00000006U
#define DDL_DMA_STREAM_7    0x00000007U
#define DDL_DMA_STREAM_ALL  0xFFFF0000U

#define DDL_DMA_DIRECTION_PERIPH_TO_MEMORY  0x00000000U        
#define DDL_DMA_DIRECTION_MEMORY_TO_PERIPH  DMA_SCFG_DIRCFG_0  
#define DDL_DMA_DIRECTION_MEMORY_TO_MEMORY  DMA_SCFG_DIRCFG_1  

#define DDL_DMA_MODE_NORMAL    0x00000000U       
#define DDL_DMA_MODE_CIRCULAR  DMA_SCFG_CIRCMEN  
#define DDL_DMA_MODE_PFCTRL    DMA_SCFG_PERFC    

#define DDL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U   
#define DDL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SCFG_DBM  

#define DDL_DMA_PERIPH_NOINCREMENT  0x00000000U     
#define DDL_DMA_PERIPH_INCREMENT    DMA_SCFG_PERIM  

#define DDL_DMA_MEMORY_NOINCREMENT  0x00000000U     
#define DDL_DMA_MEMORY_INCREMENT    DMA_SCFG_MEMIM  

#define DDL_DMA_PDATAALIGN_BYTE      0x00000000U            
#define DDL_DMA_PDATAALIGN_HALFWORD  DMA_SCFG_PERSIZECFG_0  
#define DDL_DMA_PDATAALIGN_WORD      DMA_SCFG_PERSIZECFG_1  

#define DDL_DMA_MDATAALIGN_BYTE      0x00000000U            
#define DDL_DMA_MDATAALIGN_HALFWORD  DMA_SCFG_MEMSIZECFG_0  
#define DDL_DMA_MDATAALIGN_WORD      DMA_SCFG_MEMSIZECFG_1  

#define DDL_DMA_OFFSETSIZE_PSIZE     0x00000000U         
#define DDL_DMA_OFFSETSIZE_FIXEDTO4  DMA_SCFG_PERIOSIZE  

#define DDL_DMA_PRIORITY_LOW       0x00000000U         
#define DDL_DMA_PRIORITY_MEDIUM    DMA_SCFG_PRILCFG_0  
#define DDL_DMA_PRIORITY_HIGH      DMA_SCFG_PRILCFG_1  
#define DDL_DMA_PRIORITY_VERYHIGH  DMA_SCFG_PRILCFG    

#define DDL_DMA_CHANNEL_0  0x00000000U                                                                   /* Select Channel0 of DMA Instance */
#define DDL_DMA_CHANNEL_1  DMA_SCFG_CHSEL_0                                                              /* Select Channel1 of DMA Instance */
#define DDL_DMA_CHANNEL_2  DMA_SCFG_CHSEL_1                                                              /* Select Channel2 of DMA Instance */
#define DDL_DMA_CHANNEL_3  (DMA_SCFG_CHSEL_0 | DMA_SCFG_CHSEL_1)                                         /* Select Channel3 of DMA Instance */
#define DDL_DMA_CHANNEL_4  DMA_SCFG_CHSEL_2                                                              /* Select Channel4 of DMA Instance */
#define DDL_DMA_CHANNEL_5  (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0)                                         /* Select Channel5 of DMA Instance */
#define DDL_DMA_CHANNEL_6  (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1)                                         /* Select Channel6 of DMA Instance */
#define DDL_DMA_CHANNEL_7  (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0)                      /* Select Channel7 of DMA Instance */
#if defined (DMA_SCFG_CHSEL_3)
#define DDL_DMA_CHANNEL_8   DMA_SCFG_CHSEL_3                                                              /* Select Channel8 of DMA Instance */
#define DDL_DMA_CHANNEL_9   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_0)                                         /* Select Channel9 of DMA Instance */
#define DDL_DMA_CHANNEL_10  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1)                                         /* Select Channel10 of DMA Instance */
#define DDL_DMA_CHANNEL_11  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0)                      /* Select Channel11 of DMA Instance */
#define DDL_DMA_CHANNEL_12  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2)                                         /* Select Channel12 of DMA Instance */
#define DDL_DMA_CHANNEL_13  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0)                      /* Select Channel13 of DMA Instance */
#define DDL_DMA_CHANNEL_14  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1)                      /* Select Channel14 of DMA Instance */
#define DDL_DMA_CHANNEL_15  (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0)   /* Select Channel15 of DMA Instance */
#endif /* DMA_SCFG_CHSEL_3 */

#define DDL_DMA_MBURST_SINGLE  0x00000000U                            
#define DDL_DMA_MBURST_INC4    DMA_SCFG_MBCFG_0                       
#define DDL_DMA_MBURST_INC8    DMA_SCFG_MBCFG_1                       
#define DDL_DMA_MBURST_INC16   (DMA_SCFG_MBCFG_0 | DMA_SCFG_MBCFG_1)  

#define DDL_DMA_PBURST_SINGLE  0x00000000U                            
#define DDL_DMA_PBURST_INC4    DMA_SCFG_PBCFG_0                       
#define DDL_DMA_PBURST_INC8    DMA_SCFG_PBCFG_1                       
#define DDL_DMA_PBURST_INC16   (DMA_SCFG_PBCFG_0 | DMA_SCFG_PBCFG_1)  

#define DDL_DMA_FIFOMODE_DISABLE  0x00000000U      
#define DDL_DMA_FIFOMODE_ENABLE   DMA_FCTRL_DMDEN  

#define DDL_DMA_FIFOSTATUS_0_25    0x00000000U                            
#define DDL_DMA_FIFOSTATUS_25_50   DMA_FCTRL_FSTS_0                       
#define DDL_DMA_FIFOSTATUS_50_75   DMA_FCTRL_FSTS_1                       
#define DDL_DMA_FIFOSTATUS_75_100  (DMA_FCTRL_FSTS_1 | DMA_FCTRL_FSTS_0)  
#define DDL_DMA_FIFOSTATUS_EMPTY   DMA_FCTRL_FSTS_2                       
#define DDL_DMA_FIFOSTATUS_FULL    (DMA_FCTRL_FSTS_2 | DMA_FCTRL_FSTS_0)  

#define DDL_DMA_FIFOTHRESHOLD_1_4   0x00000000U         
#define DDL_DMA_FIFOTHRESHOLD_1_2   DMA_FCTRL_FTHSEL_0  
#define DDL_DMA_FIFOTHRESHOLD_3_4   DMA_FCTRL_FTHSEL_1  
#define DDL_DMA_FIFOTHRESHOLD_FULL  DMA_FCTRL_FTHSEL    

#define DDL_DMA_CURRENTTARGETMEM0  0x00000000U     
#define DDL_DMA_CURRENTTARGETMEM1  DMA_SCFG_CTARG  

 
/* Exported macro ------------------------------------------------------------*/

#define DDL_DMA_WriteReg(__INSTANCE__,  __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

#define DDL_DMA_ReadReg(__INSTANCE__,  __REG__) READ_REG(__INSTANCE__->__REG__)

#define __DDL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)      \
(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  0 : DMA1)

#define __DDL_DMA_GET_STREAM(__STREAM_INSTANCE__)        \
(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? DDL_DMA_STREAM_0 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? DDL_DMA_STREAM_1 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? DDL_DMA_STREAM_2 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? DDL_DMA_STREAM_3 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? DDL_DMA_STREAM_4 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? DDL_DMA_STREAM_5 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? DDL_DMA_STREAM_6 : \
 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream7)) ? DDL_DMA_STREAM_7 : \
 DDL_DMA_STREAM_7)

#define __DDL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__,  __STREAM__)   \
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_0))) ? DMA1_Stream0 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_1))) ? DMA1_Stream1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_2))) ? DMA1_Stream2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_3))) ? DMA1_Stream3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_4))) ? DMA1_Stream4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_5))) ? DMA1_Stream5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_6))) ? DMA1_Stream6 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)DDL_DMA_STREAM_7))) ? DMA1_Stream7 : \
 0)


 
/* Exported functions --------------------------------------------------------*/

__STATIC_INLINE void DDL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_EN);
}

__STATIC_INLINE void DDL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_EN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_EN) == (DMA_SCFG_EN));
}

__STATIC_INLINE void DDL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
{
  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG,
             DMA_SCFG_DIRCFG | DMA_SCFG_CIRCMEN | DMA_SCFG_PERIM | DMA_SCFG_MEMIM | DMA_SCFG_PERSIZECFG | DMA_SCFG_MEMSIZECFG | DMA_SCFG_PRILCFG | DMA_SCFG_PERFC,
             Configuration);
}

__STATIC_INLINE void DDL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DIRCFG, Direction);
}

__STATIC_INLINE uint32_t DDL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DIRCFG));
}

__STATIC_INLINE void DDL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CIRCMEN | DMA_SCFG_PERFC, Mode);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CIRCMEN | DMA_SCFG_PERFC));
}

__STATIC_INLINE void DDL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERIM, IncrementMode);
}

__STATIC_INLINE uint32_t DDL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERIM));
}

__STATIC_INLINE void DDL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MEMIM, IncrementMode);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MEMIM));
}

__STATIC_INLINE void DDL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERSIZECFG, Size);
}

__STATIC_INLINE uint32_t DDL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERSIZECFG));
}

__STATIC_INLINE void DDL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MEMSIZECFG, Size);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MEMSIZECFG));
}

__STATIC_INLINE void DDL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERIOSIZE, OffsetSize);
}

__STATIC_INLINE uint32_t DDL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PERIOSIZE));
}

__STATIC_INLINE void DDL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PRILCFG, Priority);
}

__STATIC_INLINE uint32_t DDL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PRILCFG));
}

__STATIC_INLINE void DDL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDATA, DMA_NDATA_NDATA, NbData);
}

__STATIC_INLINE uint32_t DDL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDATA, DMA_NDATA_NDATA));
}

__STATIC_INLINE void DDL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CHSEL, Channel);
}

__STATIC_INLINE uint32_t DDL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CHSEL));
}

__STATIC_INLINE void DDL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MBCFG, Mburst);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_MBCFG));
}

__STATIC_INLINE void DDL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PBCFG, Pburst);
}

__STATIC_INLINE uint32_t DDL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_PBCFG));
}

__STATIC_INLINE void DDL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
{
   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CTARG, CurrentMemory);
}

__STATIC_INLINE uint32_t DDL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_CTARG));
}

__STATIC_INLINE void DDL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DBM);
}

__STATIC_INLINE void DDL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DBM);
}

__STATIC_INLINE uint32_t DDL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FSTS));
}

__STATIC_INLINE void DDL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_DMDEN);
}

__STATIC_INLINE void DDL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_DMDEN);
}

__STATIC_INLINE void DDL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FTHSEL, Threshold);
}

__STATIC_INLINE uint32_t DDL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FTHSEL));
}

__STATIC_INLINE void DDL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FTHSEL|DMA_FCTRL_DMDEN, FifoMode|FifoThreshold);
}

__STATIC_INLINE void DDL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
{
  /* Direction Memory to Periph */
  if (Direction == DDL_DMA_DIRECTION_MEMORY_TO_PERIPH)
  {
    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR, SrcAddress);
    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR, DstAddress);
  }
  /* Direction Periph to Memory and Memory to Memory */
  else
  {
    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR, SrcAddress);
    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR, DstAddress);
  }
}

__STATIC_INLINE void DDL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
{
  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR, MemoryAddress);
}

__STATIC_INLINE void DDL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
{
  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR, PeriphAddress);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
{
  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR));
}

__STATIC_INLINE uint32_t DDL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
{
  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR));
}

__STATIC_INLINE void DDL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
{
  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR, MemoryAddress);
}

__STATIC_INLINE void DDL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
  {
    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR, MemoryAddress);
  }

__STATIC_INLINE uint32_t DDL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
  {
   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PADDR));
  }

__STATIC_INLINE uint32_t DDL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
{
 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0ADDR));
}

__STATIC_INLINE void DDL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
{
  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1ADDR, DMA_M1ADDR_M1ADDR, Address);
}

__STATIC_INLINE uint32_t DDL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1ADDR);
}



__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_HTXIFLG0)==(DMA_LINTSTS_HTXIFLG0));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_HTXIFLG1)==(DMA_LINTSTS_HTXIFLG1));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_HTXIFLG2)==(DMA_LINTSTS_HTXIFLG2));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_HTXIFLG3)==(DMA_LINTSTS_HTXIFLG3));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_HTXIFLG4)==(DMA_HINTSTS_HTXIFLG4));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_HTXIFLG5)==(DMA_HINTSTS_HTXIFLG5));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_HTXIFLG6)==(DMA_HINTSTS_HTXIFLG6));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_HTXIFLG7)==(DMA_HINTSTS_HTXIFLG7));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXCIFLG0)==(DMA_LINTSTS_TXCIFLG0));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXCIFLG1)==(DMA_LINTSTS_TXCIFLG1));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXCIFLG2)==(DMA_LINTSTS_TXCIFLG2));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXCIFLG3)==(DMA_LINTSTS_TXCIFLG3));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXCIFLG4)==(DMA_HINTSTS_TXCIFLG4));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXCIFLG5)==(DMA_HINTSTS_TXCIFLG5));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXCIFLG6)==(DMA_HINTSTS_TXCIFLG6));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXCIFLG7)==(DMA_HINTSTS_TXCIFLG7));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXEIFLG0)==(DMA_LINTSTS_TXEIFLG0));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXEIFLG1)==(DMA_LINTSTS_TXEIFLG1));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXEIFLG2)==(DMA_LINTSTS_TXEIFLG2));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_TXEIFLG3)==(DMA_LINTSTS_TXEIFLG3));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXEIFLG4)==(DMA_HINTSTS_TXEIFLG4));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXEIFLG5)==(DMA_HINTSTS_TXEIFLG5));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXEIFLG6)==(DMA_HINTSTS_TXEIFLG6));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_TXEIFLG7)==(DMA_HINTSTS_TXEIFLG7));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_DMEIFLG0)==(DMA_LINTSTS_DMEIFLG0));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_DMEIFLG1)==(DMA_LINTSTS_DMEIFLG1));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_DMEIFLG2)==(DMA_LINTSTS_DMEIFLG2));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_DMEIFLG3)==(DMA_LINTSTS_DMEIFLG3));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_DMEIFLG4)==(DMA_HINTSTS_DMEIFLG4));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_DMEIFLG5)==(DMA_HINTSTS_DMEIFLG5));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_DMEIFLG6)==(DMA_HINTSTS_DMEIFLG6));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_DMEIFLG7)==(DMA_HINTSTS_DMEIFLG7));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_FEIFLG0)==(DMA_LINTSTS_FEIFLG0));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_FEIFLG1)==(DMA_LINTSTS_FEIFLG1));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_FEIFLG2)==(DMA_LINTSTS_FEIFLG2));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->LINTSTS ,DMA_LINTSTS_FEIFLG3)==(DMA_LINTSTS_FEIFLG3));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_FEIFLG4)==(DMA_HINTSTS_FEIFLG4));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_FEIFLG5)==(DMA_HINTSTS_FEIFLG5));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_FEIFLG6)==(DMA_HINTSTS_FEIFLG6));
}

__STATIC_INLINE uint32_t DDL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
{
  return (READ_BIT(DMAx->HINTSTS ,DMA_HINTSTS_FEIFLG7)==(DMA_HINTSTS_FEIFLG7));
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CHTXIFLG0);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CHTXIFLG1);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CHTXIFLG2);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CHTXIFLG3);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CHTXIFLG4);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CHTXIFLG5);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CHTXIFLG6);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CHTXIFLG7);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXCIFLG0);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXCIFLG1);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXCIFLG2);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXCIFLG3);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXCIFLG4);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXCIFLG5);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXCIFLG6);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXCIFLG7);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXEIFLG0);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXEIFLG1);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXEIFLG2);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CTXEIFLG3);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXEIFLG4);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXEIFLG5);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXEIFLG6);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CTXEIFLG7);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CDMEIFLG0);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CDMEIFLG1);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CDMEIFLG2);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CDMEIFLG3);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CDMEIFLG4);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CDMEIFLG5);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CDMEIFLG6);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CDMEIFLG7);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CFEIFLG0);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CFEIFLG1);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CFEIFLG2);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->LIFCLR , DMA_LIFCLR_CFEIFLG3);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CFEIFLG4);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CFEIFLG5);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CFEIFLG6);
}

__STATIC_INLINE void DDL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
{
  SET_BIT(DMAx->HIFCLR , DMA_HIFCLR_CFEIFLG7);
}



__STATIC_INLINE void DDL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_HTXIEN);
}

__STATIC_INLINE void DDL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXEIEN);
}

__STATIC_INLINE void DDL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXCIEN);
}

__STATIC_INLINE void DDL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DMEIEN);
}

__STATIC_INLINE void DDL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FEIEN);
}

__STATIC_INLINE void DDL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_HTXIEN);
}

__STATIC_INLINE void DDL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXEIEN);
}

__STATIC_INLINE void DDL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXCIEN);
}

__STATIC_INLINE void DDL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DMEIEN);
}

__STATIC_INLINE void DDL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FEIEN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_HTXIEN) == DMA_SCFG_HTXIEN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXEIEN) == DMA_SCFG_TXEIEN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_TXCIEN) == DMA_SCFG_TXCIEN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->SCFG, DMA_SCFG_DMEIEN) == DMA_SCFG_DMEIEN);
}

__STATIC_INLINE uint32_t DDL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{
  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCTRL, DMA_FCTRL_FEIEN) == DMA_FCTRL_FEIEN);
}

 
#if defined(USE_FULL_DDL_DRIVER)
 
uint32_t DDL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, DDL_DMA_InitTypeDef *DMA_InitStruct);
uint32_t DDL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
void DDL_DMA_StructInit(DDL_DMA_InitTypeDef *DMA_InitStruct);

#endif /* USE_FULL_DDL_DRIVER */


 
#endif /* DMA1 || DMA2 */

 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4xx_DDL_DMA_H */