g32r4xx_ddl_i2c.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_I2C_H
#define G32R4xx_DDL_I2C_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined (I2C1)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
 
/* Private constants ---------------------------------------------------------*/
 
/* Defines used to perform compute and check in the macros */
#define DDL_I2C_MAX_SPEED_STANDARD  100000U
#define DDL_I2C_MAX_SPEED_FAST      400000U
 
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)
#endif /*USE_FULL_DDL_DRIVER*/
 
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)
typedef struct
{
  uint32_t PeripheralMode;      
 
  uint32_t ClockSpeed;          
 
  uint32_t DutyCycle;           
 
#if defined(I2C_FILTER_ANFDIS) && defined(I2C_FILTER_DNFCFG)
  uint32_t AnalogFilter;        
 
  uint32_t DigitalFilter;       
 
#endif /* I2C_FILTER_ANFDIS && I2C_FILTER_DNFCFG */
  uint32_t OwnAddress1;         
 
  uint32_t TypeAcknowledge;     
 
  uint32_t OwnAddrSize;         
} DDL_I2C_InitTypeDef;

#endif /*USE_FULL_DDL_DRIVER*/
 
/* Exported constants --------------------------------------------------------*/

#define DDL_I2C_STS1_STARTFLG  I2C_STS1_STARTFLG  
#define DDL_I2C_STS1_ADDRFLG   I2C_STS1_ADDRFLG     
#define DDL_I2C_STS1_BTCFLG       I2C_STS1_BTCFLG       
#define DDL_I2C_STS1_ADDR10FLG    I2C_STS1_ADDR10FLG    
#define DDL_I2C_STS1_STOPFLG      I2C_STS1_STOPFLG      
#define DDL_I2C_STS1_RXBNEFLG     I2C_STS1_RXBNEFLG     
#define DDL_I2C_STS1_TXBEFLG      I2C_STS1_TXBEFLG      
#define DDL_I2C_STS1_BERRFLG      I2C_STS1_BERRFLG      
#define DDL_I2C_STS1_ALFLG        I2C_STS1_ALFLG        
#define DDL_I2C_STS1_AEFLG        I2C_STS1_AEFLG        
#define DDL_I2C_STS1_OVRURFLG     I2C_STS1_OVRURFLG     
#define DDL_I2C_STS1_PECEFLG      I2C_ISR_PECERR        
#define DDL_I2C_STS1_TTEFLG       I2C_ISR_TIMEOUT       
#define DDL_I2C_STS1_SMALERT      I2C_ISR_SMALERT       
#define DDL_I2C_STS2_MSFLG        I2C_STS2_MSFLG        
#define DDL_I2C_STS2_BUSBSYFLG    I2C_STS2_BUSBSYFLG    
#define DDL_I2C_STS2_TRFLG        I2C_STS2_TRFLG        
#define DDL_I2C_STS2_GENCALLFLG   I2C_STS2_GENCALLFLG   
#define DDL_I2C_STS2_SMBDADDRFLG  I2C_STS2_SMBDADDRFLG  
#define DDL_I2C_STS2_SMMHADDR     I2C_STS2_SMMHADDR     
#define DDL_I2C_STS2_DUALADDRFLG  I2C_STS2_DUALADDRFLG  

 
/* Master mode events */
#define DDL_I2C_EVENT_MASTER_MODE_SELECT                0x00030001u /* BUSBSYFLG, MSFLG and STARTFLG flag */
#define DDL_I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED  0x00070082u /* BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */
#define DDL_I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED     0x00030002u /* BUSBSYFLG, MSFLG and ADDRFLG flags */
#define DDL_I2C_EVENT_MASTER_MODE_ADDRESS10             0x00030008u /* BUSBSYFLG, MSFLG and ADDR10FLG flags */
#define DDL_I2C_EVENT_MASTER_BYTE_RECEIVED              0x00030040u /* BUSBSYFLG, MSFLG and RXBNEFLG flags */
#define DDL_I2C_EVENT_MASTER_BYTE_TRANSMITTING          0x00070080u /* TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */
#define DDL_I2C_EVENT_MASTER_BYTE_TRANSMITTED           0x00070084u /* TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */
 
/* Slave address matched events */
#define DDL_I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED           0x00020002u /* BUSBSYFLG and ADDRFLG flags */
#define DDL_I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED        0x00060082u /* TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */
#define DDL_I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED     0x00820000u /* DUALF and BUSBSYFLG flags */
#define DDL_I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED  0x00860080u /* DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */
#define DDL_I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED         0x00120000u /* GENCALL and BUSBSYFLG flags */
 
/* Slave receiver mode */
#define DDL_I2C_EVENT_SLAVE_BYTE_RECEIVED   0x00020040u /* BUSBSYFLG and RXBNEFLG flags */
#define DDL_I2C_EVENT_SLAVE_BYTE_RECEIVED1  0x00820040u /* DUALADDRFLG, BUSBSYFLG and RXBNEFLG flags */
#define DDL_I2C_EVENT_SLAVE_BYTE_RECEIVED2  0x00120040u /* GENCALLFLG, BUSBSYFLG and RXBNEFLG flags */
#define DDL_I2C_EVENT_SLAVE_STOP_DETECTED   0x00000010u /* STOPFLG flag */
 
/* Slave transmitter mode */
#define DDL_I2C_EVENT_SLAVE_BYTE_TRANSMITTED   0x00060084u /* TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
#define DDL_I2C_EVENT_SLAVE_BYTE_TRANSMITTED1  0x00860084u /* DUALADDRFLG, TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
#define DDL_I2C_EVENT_SLAVE_BYTE_TRANSMITTED2  0x00160084u /* GENCALLFLG, TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
#define DDL_I2C_EVENT_SLAVE_BYTE_TRANSMITTING  0x00060080u /* TRFLG, BUSBSYFLG and TXBEFLG flags */
#define DDL_I2C_EVENT_SLAVE_ACK_FAILURE        0x00000400u /* AEFLG flag */


#define DDL_I2C_CTRL2_EVIEN   I2C_CTRL2_EVIEN   
#define DDL_I2C_CTRL2_BUFIEN  I2C_CTRL2_BUFIEN  
#define DDL_I2C_CTRL2_ERRIEN  I2C_CTRL2_ERRIEN  
 
#if defined(I2C_FILTER_ANFDIS)
#define DDL_I2C_ANALOGFILTER_ENABLE   0x00000000U        
#define DDL_I2C_ANALOGFILTER_DISABLE  I2C_FILTER_ANFDIS  
 
#endif
#define DDL_I2C_OWNADDRESS1_7BIT   0x00004000U                                   
#define DDL_I2C_OWNADDRESS1_10BIT  (uint32_t)(I2C_SADDR1_ADDRLEN | 0x00004000U)  

#define DDL_I2C_DUTYCYCLE_2     0x00000000U           
#define DDL_I2C_DUTYCYCLE_16_9  I2C_CLKCTRL_FDUTYCFG  

#define DDL_I2C_CLOCK_SPEED_STANDARD_MODE  0x00000000U           
#define DDL_I2C_CLOCK_SPEED_FAST_MODE      I2C_CLKCTRL_SPEEDCFG  

#define DDL_I2C_MODE_I2C               0x00000000U                                                        
#define DDL_I2C_MODE_SMBUS_HOST        (uint32_t)(I2C_CTRL1_SMBEN | I2C_CTRL1_SMBTCFG | I2C_CTRL1_ARPEN)  
#define DDL_I2C_MODE_SMBUS_DEVICE      I2C_CTRL1_SMBEN                                                    
#define DDL_I2C_MODE_SMBUS_DEVICE_ARP  (uint32_t)(I2C_CTRL1_SMBEN | I2C_CTRL1_ARPEN)                      

#define DDL_I2C_ACK   I2C_CTRL1_ACKEN  
#define DDL_I2C_NACK  0x00000000U      

#define DDL_I2C_DIRECTION_WRITE  I2C_STS2_TRFLG  
#define DDL_I2C_DIRECTION_READ   0x00000000U     

 
/* Exported macro ------------------------------------------------------------*/


#define DDL_I2C_WriteReg(__INSTANCE__,  __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

#define DDL_I2C_ReadReg(__INSTANCE__,  __REG__) READ_REG(__INSTANCE__->__REG__)


#define __DDL_I2C_FREQ_HZ_TO_MHZ(__PCLK__)         (uint32_t)((__PCLK__)/1000000U)

#define __DDL_I2C_FREQ_MHZ_TO_HZ(__PCLK__)         (uint32_t)((__PCLK__)*1000000U)

#define __DDL_I2C_RISE_TIME(__FREQRANGE__,         __SPEED__)                    (uint32_t)(((__SPEED__) <= DDL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))

#define __DDL_I2C_SPEED_TO_CCR(__PCLK__,           __SPEED__, __DUTYCYCLE__)       (uint32_t)(((__SPEED__) <= DDL_I2C_MAX_SPEED_STANDARD)? \
                                                                                  (__DDL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
                                                                                  (__DDL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))

#define __DDL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__,  __SPEED__)             (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CLKCTRL_CLKS) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))

#define __DDL_I2C_SPEED_FAST_TO_CCR(__PCLK__,      __SPEED__, __DUTYCYCLE__)  (uint32_t)(((__DUTYCYCLE__) == DDL_I2C_DUTYCYCLE_2)? \
                                                                            (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CLKCTRL_CLKS) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
                                                                            (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CLKCTRL_CLKS) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))

#define __DDL_I2C_10BIT_ADDRESS(__ADDRESS__)       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))

#define __DDL_I2C_10BIT_HEADER_WRITE(__ADDRESS__)  ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))

#define __DDL_I2C_10BIT_HEADER_READ(__ADDRESS__)   ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))

 
/* Exported functions --------------------------------------------------------*/



__STATIC_INLINE void DDL_I2C_Enable(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_I2CEN);
}

__STATIC_INLINE void DDL_I2C_Disable(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_I2CEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_I2CEN) == (I2C_CTRL1_I2CEN));
}
 
#if defined(I2C_FILTER_ANFDIS) && defined(I2C_FILTER_DNFCFG)
__STATIC_INLINE void DDL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
{
  MODIFY_REG(I2Cx->FILTER, I2C_FILTER_ANFDIS | I2C_FILTER_DNFCFG, AnalogFilter | DigitalFilter);
}
#endif /* I2C_FILTER_ANFDIS && I2C_FILTER_DNFCFG */
 
#if defined(I2C_FILTER_DNFCFG)
__STATIC_INLINE void DDL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
{
  MODIFY_REG(I2Cx->FILTER, I2C_FILTER_DNFCFG, DigitalFilter);
}

__STATIC_INLINE uint32_t DDL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->FILTER, I2C_FILTER_DNFCFG));
}
#endif /* I2C_FILTER_DNFCFG */
 
#if defined(I2C_FILTER_ANFDIS)
__STATIC_INLINE void DDL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->FILTER, I2C_FILTER_ANFDIS);
}

__STATIC_INLINE void DDL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->FILTER, I2C_FILTER_ANFDIS);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->FILTER, I2C_FILTER_ANFDIS) == (I2C_FILTER_ANFDIS));
}
#endif /* I2C_FILTER_ANFDIS */

__STATIC_INLINE void DDL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_CLKSTRETCHD);
}

__STATIC_INLINE void DDL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_CLKSTRETCHD);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_CLKSTRETCHD) != (I2C_CTRL1_CLKSTRETCHD));
}

__STATIC_INLINE void DDL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_SRBEN);
}

__STATIC_INLINE void DDL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_SRBEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_SRBEN) == (I2C_CTRL1_SRBEN));
}

__STATIC_INLINE void DDL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
{
  MODIFY_REG(I2Cx->SADDR1, I2C_SADDR1_ADDR0 | I2C_SADDR1_ADDR1_7 | I2C_SADDR1_ADDR8_9 | I2C_SADDR1_ADDRLEN, OwnAddress1 | OwnAddrSize);
}

__STATIC_INLINE void DDL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
{
  MODIFY_REG(I2Cx->SADDR2, I2C_SADDR2_ADDR2, OwnAddress2);
}

__STATIC_INLINE void DDL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->SADDR2, I2C_SADDR2_ADDRNUM);
}

__STATIC_INLINE void DDL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->SADDR2, I2C_SADDR2_ADDRNUM);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->SADDR2, I2C_SADDR2_ADDRNUM) == (I2C_SADDR2_ADDRNUM));
}

__STATIC_INLINE void DDL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
{
  MODIFY_REG(I2Cx->CTRL2, I2C_CTRL2_CLKFCFG, __DDL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
}

__STATIC_INLINE uint32_t DDL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(__DDL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CTRL2, I2C_CTRL2_CLKFCFG)));
}

__STATIC_INLINE void DDL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
{
  MODIFY_REG(I2Cx->CLKCTRL, I2C_CLKCTRL_FDUTYCFG, DutyCycle);
}

__STATIC_INLINE uint32_t DDL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->CLKCTRL, I2C_CLKCTRL_FDUTYCFG));
}

__STATIC_INLINE void DDL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
{
  MODIFY_REG(I2Cx->CLKCTRL, I2C_CLKCTRL_SPEEDCFG, ClockSpeedMode);
}

__STATIC_INLINE uint32_t DDL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->CLKCTRL, I2C_CLKCTRL_SPEEDCFG));
}

__STATIC_INLINE void DDL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
{
  MODIFY_REG(I2Cx->RISETMAX, I2C_RISETMAX_RISETMAX, RiseTime);
}

__STATIC_INLINE uint32_t DDL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->RISETMAX, I2C_RISETMAX_RISETMAX));
}

__STATIC_INLINE void DDL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
{
  MODIFY_REG(I2Cx->CLKCTRL, I2C_CLKCTRL_CLKS, ClockPeriod);
}

__STATIC_INLINE uint32_t DDL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->CLKCTRL, I2C_CLKCTRL_CLKS));
}

__STATIC_INLINE void DDL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
                                        uint32_t DutyCycle)
{
  uint32_t freqrange = 0x0U;
  uint32_t clockconfig = 0x0U;
 
  /* Compute frequency range */
  freqrange = __DDL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
 
  /* Configure I2Cx: Frequency range register */
  MODIFY_REG(I2Cx->CTRL2, I2C_CTRL2_CLKFCFG, freqrange);
 
  /* Configure I2Cx: Rise Time register */
  MODIFY_REG(I2Cx->RISETMAX, I2C_RISETMAX_RISETMAX, __DDL_I2C_RISE_TIME(freqrange, ClockSpeed));
 
  /* Configure Speed mode, Duty Cycle and Clock control register value */
  if (ClockSpeed > DDL_I2C_MAX_SPEED_STANDARD)
  {
    /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
    clockconfig = DDL_I2C_CLOCK_SPEED_FAST_MODE                                          | \
                  __DDL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle)        | \
                  DutyCycle;
  }
  else
  {
    /* Set Speed mode at standard for Clock Speed request in standard clock range */
    clockconfig = DDL_I2C_CLOCK_SPEED_STANDARD_MODE                                      | \
                  __DDL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
  }
 
  /* Configure I2Cx: Clock control register */
  MODIFY_REG(I2Cx->CLKCTRL, (I2C_CLKCTRL_SPEEDCFG | I2C_CLKCTRL_FDUTYCFG | I2C_CLKCTRL_CLKS), clockconfig);
}

__STATIC_INLINE void DDL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
{
  MODIFY_REG(I2Cx->CTRL1, I2C_CTRL1_SMBEN | I2C_CTRL1_SMBTCFG | I2C_CTRL1_ARPEN, PeripheralMode);
}

__STATIC_INLINE uint32_t DDL_I2C_GetMode(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->CTRL1, I2C_CTRL1_SMBEN | I2C_CTRL1_SMBTCFG | I2C_CTRL1_ARPEN));
}

__STATIC_INLINE void DDL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_ALERTEN);
}

__STATIC_INLINE void DDL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_ALERTEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_ALERTEN) == (I2C_CTRL1_ALERTEN));
}

__STATIC_INLINE void DDL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_PECEN);
}

__STATIC_INLINE void DDL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_PECEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_PECEN) == (I2C_CTRL1_PECEN));
}



__STATIC_INLINE void DDL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN);
}

__STATIC_INLINE void DDL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN) == (I2C_CTRL2_DMAEN));
}

__STATIC_INLINE void DDL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN);
}

__STATIC_INLINE void DDL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_DMAEN) == (I2C_CTRL2_DMAEN));
}

__STATIC_INLINE uint32_t DDL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
{
  return (uint32_t) & (I2Cx->DATA);
}



__STATIC_INLINE void DDL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE void DDL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN) == (I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN));
}

__STATIC_INLINE void DDL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE void DDL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN) == (I2C_CTRL2_EVIEN | I2C_CTRL2_BUFIEN));
}

__STATIC_INLINE void DDL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN);
}

__STATIC_INLINE void DDL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_EVIEN) == (I2C_CTRL2_EVIEN));
}

__STATIC_INLINE void DDL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE void DDL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_BUFIEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_BUFIEN) == (I2C_CTRL2_BUFIEN));
}

__STATIC_INLINE void DDL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_ERRIEN);
}

__STATIC_INLINE void DDL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_ERRIEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_ERRIEN) == (I2C_CTRL2_ERRIEN));
}



__STATIC_INLINE uint32_t DDL_I2C_ReadEventStatus(I2C_TypeDef *I2Cx, uint32_t i2cEvent)
{
    /* Read STS1 and STS2. STS1 lower 16 bits, STS2 lower 16 bits shifted left 16 */
    uint32_t flag1 = READ_BIT(I2Cx->STS1, 0x0000FFFFUL); /* Read all STS1 bits */
    uint32_t flag2 = READ_BIT(I2Cx->STS2, 0x0000FFFFUL); /* Read all STS2 bits */
 
    /* Shift STS2 read result left by 16 to match the same position as i2cEvent */
    flag2 <<= 16;
 
    /* Combine STS1 and STS2 as a 24-bit event status */
    uint32_t lastevent = (flag1 | flag2) & 0x00FFFFFFUL;
 
    /* Check if all bits in i2cEvent are set */
    if ((lastevent & i2cEvent) == i2cEvent)
    {
        return 1UL;
    }
 
    return 0UL;
}

__STATIC_INLINE uint32_t I2C_ReadLastEvent(I2C_TypeDef *I2Cx)
{
    /* Read STS1 and STS2. STS1 lower 16 bits, STS2 lower 16 bits shifted left 16 */
    uint32_t flag1 = READ_BIT(I2Cx->STS1, 0x0000FFFFUL); /* Read all STS1 bits */
    uint32_t flag2 = READ_BIT(I2Cx->STS2, 0x0000FFFFUL); /* Read all STS2 bits */
 
    /* Shift STS2 read result left by 16 to match the same position as events define */
    flag2 <<= 16;
 
    /* Combine STS1 and STS2 as a 24-bit event status */
    uint32_t lastevent = (flag1 | flag2) & 0x00FFFFFFUL;
 
    return lastevent;
}



__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_START(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_STARTFLG) == (I2C_STS1_STARTFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_ADDRFLG) == (I2C_STS1_ADDRFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
{
  __IO uint32_t tmpreg;
  tmpreg = I2Cx->STS1;
  (void) tmpreg;
  tmpreg = I2Cx->STS2;
  (void) tmpreg;
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_BTCFLG) == (I2C_STS1_BTCFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_ADDR10FLG) == (I2C_STS1_ADDR10FLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_STOPFLG) == (I2C_STS1_STOPFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
{
  __IO uint32_t tmpreg;
  tmpreg = I2Cx->STS1;
  (void) tmpreg;
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_I2CEN);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_RXBNEFLG) == (I2C_STS1_RXBNEFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_TXBEFLG) == (I2C_STS1_TXBEFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_BERRFLG) == (I2C_STS1_BERRFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_BERRFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_ALFLG) == (I2C_STS1_ALFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_ALFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_AEFLG) == (I2C_STS1_AEFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_AEFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_OVRURFLG) == (I2C_STS1_OVRURFLG));
}

__STATIC_INLINE void DDL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_OVRURFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_PECEFLG) == (I2C_STS1_PECEFLG));
}

__STATIC_INLINE void DDL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_PECEFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_TTEFLG) == (I2C_STS1_TTEFLG));
}

__STATIC_INLINE void DDL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_TTEFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS1, I2C_STS1_SMBALTFLG) == (I2C_STS1_SMBALTFLG));
}

__STATIC_INLINE void DDL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->STS1, I2C_STS1_SMBALTFLG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_MSFLG) == (I2C_STS2_MSFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_BUSBSYFLG) == (I2C_STS2_BUSBSYFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_GENCALLFLG) == (I2C_STS2_GENCALLFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_SMBDADDRFLG) == (I2C_STS2_SMBDADDRFLG));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_SMMHADDR) == (I2C_STS2_SMMHADDR));
}

__STATIC_INLINE uint32_t DDL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->STS2, I2C_STS2_DUALADDRFLG) == (I2C_STS2_DUALADDRFLG));
}



__STATIC_INLINE void DDL_I2C_EnableReset(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_SWRST);
}

__STATIC_INLINE void DDL_I2C_DisableReset(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_SWRST);
}

__STATIC_INLINE uint32_t DDL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_SWRST) == (I2C_CTRL1_SWRST));
}

__STATIC_INLINE void DDL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
{
  MODIFY_REG(I2Cx->CTRL1, I2C_CTRL1_ACKEN, TypeAcknowledge);
}

__STATIC_INLINE void DDL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_START);
}

__STATIC_INLINE void DDL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_STOP);
}

__STATIC_INLINE void DDL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_ACKPOS);
}

__STATIC_INLINE void DDL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_ACKPOS);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_ACKPOS) == (I2C_CTRL1_ACKPOS));
}

__STATIC_INLINE uint32_t DDL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->STS2, I2C_STS2_TRFLG));
}

__STATIC_INLINE void DDL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL2, I2C_CTRL2_LTCFG);
}

__STATIC_INLINE void DDL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL2, I2C_CTRL2_LTCFG);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL2, I2C_CTRL2_LTCFG) == (I2C_CTRL2_LTCFG));
}

__STATIC_INLINE void DDL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
  SET_BIT(I2Cx->CTRL1, I2C_CTRL1_PEC);
}

__STATIC_INLINE void DDL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
  CLEAR_BIT(I2Cx->CTRL1, I2C_CTRL1_PEC);
}

__STATIC_INLINE uint32_t DDL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
  return (READ_BIT(I2Cx->CTRL1, I2C_CTRL1_PEC) == (I2C_CTRL1_PEC));
}

__STATIC_INLINE uint32_t DDL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
  return (uint32_t)(READ_BIT(I2Cx->STS2, I2C_STS2_PECVALUE) >> I2C_STS2_PECVALUE_Pos);
}

__STATIC_INLINE uint8_t DDL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
{
  return (uint8_t)(READ_BIT(I2Cx->DATA, I2C_DATA_DATA));
}

__STATIC_INLINE void DDL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
{
  MODIFY_REG(I2Cx->DATA, I2C_DATA_DATA, Data);
}

 
#if defined(USE_FULL_DDL_DRIVER)
 
uint32_t DDL_I2C_Init(I2C_TypeDef *I2Cx, DDL_I2C_InitTypeDef *I2C_InitStruct);
uint32_t DDL_I2C_DeInit(I2C_TypeDef *I2Cx);
void DDL_I2C_StructInit(DDL_I2C_InitTypeDef *I2C_InitStruct);

#endif /* USE_FULL_DDL_DRIVER */



 
#endif /* I2C1 */

 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4xx_DDL_I2C_H */