g32r4xx_ddl_nvic.c

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#if defined(USE_FULL_DDL_DRIVER)
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx_ddl_nvic.h"
#include "g32r4xx_ddl_rcm.h"
#ifdef  USE_FULL_ASSERT
#include "g32_assert.h"
#else
#define ASSERT_PARAM(_PARAM_) ((void)0U)
#endif



 
#define DDL_AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
#define DDL_VECTOR_SIZE           39
 
/* Private function prototypes -----------------------------------------------*/
 
/* Exported functions --------------------------------------------------------*/



void DDL_NVIC_ConfigPriorityGroup(uint32_t priorityGroup)
{
    SCB->AIRCR = DDL_AIRCR_VECTKEY_MASK | priorityGroup;
}

void DDL_NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority)
{
    uint32_t tempPriority, tempPrePri, tempSubPri;
    uint32_t priorityGrp;
 
    /* Get priority group */
    priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
 
    /* get pre-emption priority and subpriority */
    switch(priorityGrp)
    {
        case DDL_NVIC_PRIORITY_GROUP_0:
            tempPrePri = 0;
            tempSubPri = 4;
            break;
 
        case DDL_NVIC_PRIORITY_GROUP_1:
            tempPrePri = 1;
            tempSubPri = 3;
            break;
 
        case DDL_NVIC_PRIORITY_GROUP_2:
            tempPrePri = 2;
            tempSubPri = 2;
            break;
 
        case DDL_NVIC_PRIORITY_GROUP_3:
            tempPrePri = 3;
            tempSubPri = 1;
            break;
 
        case DDL_NVIC_PRIORITY_GROUP_4:
            tempPrePri = 4;
            tempSubPri = 0;
            break;
 
        default:
            DDL_NVIC_ConfigPriorityGroup(DDL_NVIC_PRIORITY_GROUP_0);
            tempPrePri = 0;
            tempSubPri = 4;
            break;
    }
 
    tempPrePri = 4 - tempPrePri;
    tempSubPri = 4 - tempSubPri;
    tempPriority = preemptionPriority << tempPrePri;
    tempPriority |= subPriority & (0x0f >> tempSubPri);
    tempPriority <<= 4;
    NVIC->IPR[irq] = (uint8_t)tempPriority;
 
    /* enable the selected IRQ */
    NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
}

void DDL_NVIC_DisableIRQRequest(IRQn_Type irq)
{
    /* disable the selected IRQ.*/
    NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
}

void DDL_NVIC_ConfigVectorTable(uint32_t vectTab, uint32_t offset)
{
    SCB->VTOR = vectTab | (offset & (uint32_t)0x1FFFFF80);
}

void DDL_SysTick_ConfigCLKSource(uint32_t clkSource)
{
    if (clkSource == DDL_SYSTICK_CLK_SOURCE_HCLK)
    {
        SysTick->CTRL |= (uint32_t)BIT2;
    }
    else
    {
        SysTick->CTRL &= (uint32_t)(~BIT2);
    }
}
 
#ifdef VECT_TAB_SRAM
ErrorStatus DDL_Interrupt_Register(IRQn_Type irqn, Interrupt_Handler new_handler)
{
    uint32_t *vectors = (uint32_t *)SCB->VTOR;
    uint32_t vtor_addr = (uint32_t)SCB->VTOR;
    
    /* IRQ range check */
    if (irqn < -15 || irqn >= DDL_VECTOR_SIZE)
    {
        return ERROR;
    }
    
    /* VTOR region check */
    if (!((vtor_addr >= 0x20000000u && vtor_addr <= 0x20003FFFu) ||
          (vtor_addr <= 0x00007FFFu)))
    {
        return ERROR;
    }
 
    vectors[irqn+16] = (uint32_t)new_handler;
    __DSB();
 
    return SUCCESS;
}
 
#endif




 
#endif