g32r4xx_ddl_rcm.c

Go to the documentation of this file.

#if defined(USE_FULL_DDL_DRIVER)
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx_ddl_rcm.h"
#ifdef  USE_FULL_ASSERT
    #include "g32_assert.h"
#else
    #define ASSERT_PARAM(_PARAM_) ((void)0U)
#endif
 
#if defined(RCM)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#define DDL_RCM_TIMEOUT_VALUE       50000U
 
/* Private function prototypes -----------------------------------------------*/
uint32_t RCM_GetSystemClockFreq(void);
uint32_t RCM_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCM_GetPCLKClockFreq(uint32_t HCLK_Frequency);
uint32_t RCM_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
 
/* Exported functions --------------------------------------------------------*/


ErrorStatus DDL_RCM_DeInit(void)
{
    __IO uint32_t vl_mask;
    volatile uint32_t timeout = DDL_RCM_TIMEOUT_VALUE;
    ErrorStatus status = SUCCESS;
 
    /* Set HSIEN bit */
    DDL_RCM_HSI_Enable();
 
    /* Wait for HSI READY bit */
    timeout = DDL_RCM_TIMEOUT_VALUE;
    while (DDL_RCM_HSI_IsReady() != 1U)
    {
        if (timeout-- == 0)
        {
            status = ERROR;
            return status;
        }
    }
 
    /* Reset CFG register */
    DDL_RCM_WriteReg(SCCR, 0x00000000U);
 
    /* Switch system clock source to HSI by configuring MCCR. */
    DDL_RCM_WriteReg(MCCR, 0x00000001U);
 
    /* Disable automatic clock switch back from HSI. */
    DDL_RCM_WriteReg(MCCR, 0x00000000U);
 
    /* Wait for the system clock switch to complete and stabilize. */
    timeout = DDL_RCM_TIMEOUT_VALUE;
    while ((READ_BIT(RCM->MCCR, RCM_MCCR_SWST) >> RCM_MCCR_SWST_Pos) != 0U)
    {
        if (timeout-- == 0)
        {
            status = ERROR;
            return status;
        }
    }
 
    /* Read CTRL register */
    vl_mask = DDL_RCM_ReadReg(RCCR);
 
    /* Reset HSEEN, PLLEN, CSSEN bits */
    CLEAR_BIT(vl_mask, (RCM_RCCR_HSEON | RCM_RCCR_PLLON | RCM_RCCR_CSSON));
 
    /* Write new value in CTRL register */
    DDL_RCM_WriteReg(RCCR, vl_mask);
 
    /* Wait for PLL READY bit to be reset */
    timeout = DDL_RCM_TIMEOUT_VALUE;
    while (DDL_RCM_PLL_IsReady() != 0U)
    {
        if (timeout-- == 0)
        {
            status = ERROR;
            return status;
        }
    }
 
    /* Reset PLLCR register */
    DDL_RCM_WriteReg(PLLCR, RCM_PLLCR_RST_VALUE);
 
    /* Disable all interrupts */
    CLEAR_BIT(RCM->CIER,
              (RCM_CIER_LSIRDYIE | RCM_CIER_LSERDYIE | RCM_CIER_HSIRDYIE | \
               RCM_CIER_HSERDYIE | RCM_CIER_PLLRDYIE));
 
    /* Clear all interrupt flags */
    SET_BIT(RCM->CICR,
            (RCM_CICR_LSIRDYF | RCM_CICR_LSERDYF | RCM_CICR_HSIRDYF | \
             RCM_CICR_HSERDYF | RCM_CICR_PLLRDYF | RCM_CICR_HSECSSF | \
             RCM_CICR_LSECSSF));
 
    /* Reset all RSTFLGCLR flags */
    SET_BIT(RCM->RSTCSR,
            (RCM_RSTCSR_OPRSTF | RCM_RSTCSR_PINRSTF | RCM_RSTCSR_PORRSTF | \
             RCM_RSTCSR_SFTRSTF | RCM_RSTCSR_IWDTRSTF | RCM_RSTCSR_WWDTRSTF));
 
    return status;
}



void DDL_RCM_GetSystemClocksFreq(DDL_RCM_ClocksTypeDef* RCM_Clocks)
{
    /* Get SYSCLK frequency */
    RCM_Clocks->SYSCLK_Frequency = RCM_GetSystemClockFreq();
 
    /* HCLK clock frequency */
    RCM_Clocks->HCLK_Frequency   = RCM_GetHCLKClockFreq(RCM_Clocks->SYSCLK_Frequency);
 
    /* PCLK clock frequency */
    RCM_Clocks->PCLK_Frequency  = RCM_GetPCLKClockFreq(RCM_Clocks->HCLK_Frequency);
}




uint32_t RCM_GetSystemClockFreq(void)
{
    uint32_t frequency = 0U;
 
    /* Get SYSCLK source -------------------------------------------------------*/
    switch (DDL_RCM_GetSysClkSource())
    {
        case DDL_RCM_SYS_CLKSOURCE_HSI:  /* HSI used as system clock source */
            frequency = HSI_VALUE;
            break;
 
        case DDL_RCM_SYS_CLKSOURCE_HSE:  /* HSE used as system clock source */
            frequency = HSE_VALUE;
            break;
 
        case DDL_RCM_SYS_CLKSOURCE_PLL:  /* PLL used as system clock source */
            frequency = RCM_PLL_GetFreqDomain_SYS(DDL_RCM_SYS_CLKSOURCE_PLL);
            break;
 
        default:
            frequency = HSI_VALUE;
            break;
    }
 
    return frequency;
}

uint32_t RCM_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
    /* HCLK clock frequency */
    return __DDL_RCM_CALC_HCLK_FREQ(SYSCLK_Frequency, DDL_RCM_GetAHBPrescaler());
}

uint32_t RCM_GetPCLKClockFreq(uint32_t HCLK_Frequency)
{
    /* PCLK clock frequency */
    return __DDL_RCM_CALC_PCLK_FREQ(HCLK_Frequency, DDL_RCM_GetAPBPrescaler());
}

uint32_t RCM_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
{
    uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U, pllprescaler = 0U;
 
    /* SYSCLK = ((HSE_VALUE or HSI_VALUE / PLLP) * PLLMUL */
    pllsource = DDL_RCM_PLL_GetClkSource();
 
    switch (pllsource)
    {
        case DDL_RCM_PLL_CLKSOURCE_HSI:  /* HSI used as PLL clock source */
            pllinputfreq = HSI_VALUE;
            break;
 
        case DDL_RCM_PLL_CLKSOURCE_HSE:  /* HSE used as PLL clock source */
            pllinputfreq = HSE_VALUE;
            break;
 
        default:
            pllinputfreq = HSI_VALUE;
            break;
    }
 
    if (SYSCLK_Source == DDL_RCM_SYS_CLKSOURCE_PLL)
    {
        pllprescaler = (DDL_RCM_PLL_GetPrescaler() >> RCM_PLLCR_PLLP_Pos);
 
        if(pllprescaler == 0)
        {
            pllprescaler = 1;
        }
 
        plloutputfreq = __DDL_RCM_CALC_PLLCLK_FREQ(pllinputfreq, \
        pllprescaler, DDL_RCM_PLL_GetMultiplier());
    }
 
    return plloutputfreq;
}


 
#endif /* defined(RCM) */

 
#endif /* USE_FULL_DDL_DRIVER */