Header file of RCM DDL module. More...

#include "g32r4xx.h"

Data Structures
struct	DDL_RCM_ClocksTypeDef
	RCM Clocks Frequency Structure. More...

Macros
#define	HSE_VALUE 8000000U
#define	HSI_VALUE 8000000U
#define	LSE_VALUE 32768U
#define	LSI_VALUE 32000U
#define	DDL_RCM_INT_LSIRDYFLG RCM_CICR_LSIRDYF
#define	DDL_RCM_INT_LSERDYFLG RCM_CICR_LSERDYF
#define	DDL_RCM_INT_HSIRDYFLG RCM_CICR_HSIRDYF
#define	DDL_RCM_INT_HSERDYFLG RCM_CICR_HSERDYF
#define	DDL_RCM_INT_PLLRDYFLG RCM_CICR_PLLRDYF
#define	DDL_RCM_INT_HSECSSFLG RCM_CICR_HSECSSF
#define	DDL_RCM_INT_LSECSSFLG RCM_CICR_LSECSSF
#define	DDL_RCM_RSTCSR_OPRSTFLG RCM_RSTCSR_OPRSTF
#define	DDL_RCM_RSTCSR_PINRSTFLG RCM_RSTCSR_PINRSTF
#define	DDL_RCM_RSTCSR_PORRSTFLG RCM_RSTCSR_PORRSTF
#define	DDL_RCM_RSTCSR_SFTRSTFLG RCM_RSTCSR_SFTRSTF
#define	DDL_RCM_RSTCSR_IWDTRSTFLG RCM_RSTCSR_IWDTRSTF
#define	DDL_RCM_RSTCSR_WWDTRSTFLG RCM_RSTCSR_WWDTRSTF
#define	DDL_RCM_INT_LSIRDYEN RCM_CIER_LSIRDYIE
#define	DDL_RCM_INT_LSERDYEN RCM_CIER_LSERDYIE
#define	DDL_RCM_INT_HSIRDYEN RCM_CIER_HSIRDYIE
#define	DDL_RCM_INT_HSERDYEN RCM_CIER_HSERDYIE
#define	DDL_RCM_INT_PLLRDYEN RCM_CIER_PLLRDYIE
#define	DDL_RCM_INT_HSECSSEN RCM_CIER_HSECSSIE
#define	DDL_RCM_INT_LSECSSEN RCM_CIER_LSECSSIE
#define	DDL_RCM_SYS_CLKSOURCE_HSI (0x00000000U)
#define	DDL_RCM_SYS_CLKSOURCE_HSE (0x00000001U)
#define	DDL_RCM_SYS_CLKSOURCE_PLL (0x00000002U)
#define	DDL_RCM_AHB_DIV_1 (RCM_SCCR_HDIV_0)
#define	DDL_RCM_AHB_DIV_2 (RCM_SCCR_HDIV_3)
#define	DDL_RCM_AHB_DIV_4 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_0)
#define	DDL_RCM_AHB_DIV_8 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_1)
#define	DDL_RCM_AHB_DIV_16 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_1 \| RCM_SCCR_HDIV_0)
#define	DDL_RCM_AHB_DIV_32 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_2)
#define	DDL_RCM_AHB_DIV_64 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_2 \| RCM_SCCR_HDIV_0)
#define	DDL_RCM_AHB_DIV_128 (RCM_SCCR_HDIV_3 \| RCM_SCCR_HDIV_2 \| RCM_SCCR_HDIV_1)
#define	DDL_RCM_AHB_DIV_256 (RCM_SCCR_HDIV)
#define	DDL_RCM_APB_DIV_1 (0x00000000U)
#define	DDL_RCM_APB_DIV_2 (RCM_SCCR_PDIV_2)
#define	DDL_RCM_APB_DIV_4 (RCM_SCCR_PDIV_2 \| RCM_SCCR_PDIV_0)
#define	DDL_RCM_APB_DIV_8 (RCM_SCCR_PDIV_2 \| RCM_SCCR_PDIV_1)
#define	DDL_RCM_APB_DIV_16 (RCM_SCCR_PDIV)
#define	DDL_RCM_AHB_RESET_DMA RCM_AHBRST_DMARST
#define	DDL_RCM_AHB_RESET_GPIO RCM_AHBRST_GPIORST
#define	DDL_RCM_AHB_RESET_ADC1 RCM_AHBRST_ADC1RST
#define	DDL_RCM_AHB_RESET_ADC2 RCM_AHBRST_ADC2RST
#define	DDL_RCM_AHB_RESET_ADC3 RCM_AHBRST_ADC3RST
#define	DDL_RCM_AHB_RESET_FLASH RCM_AHBRST_FLASHRST
#define	DDL_RCM_APB_RESET_TMR1 RCM_APBRST_TMR1RST
#define	DDL_RCM_APB_RESET_TMR2 RCM_APBRST_TMR2RST
#define	DDL_RCM_APB_RESET_TMR3 RCM_APBRST_TMR3RST
#define	DDL_RCM_APB_RESET_TMR4 RCM_APBRST_TMR4RST
#define	DDL_RCM_APB_RESET_SPI RCM_APBRST_SPIRST
#define	DDL_RCM_APB_RESET_USART1 RCM_APBRST_USART1RST
#define	DDL_RCM_APB_RESET_USART2 RCM_APBRST_USART2RST
#define	DDL_RCM_APB_RESET_I2C RCM_APBRST_I2CRST
#define	DDL_RCM_APB_RESET_TS RCM_APBRST_TSRST
#define	DDL_RCM_APB_RESET_EINT RCM_APBRST_EINTRST
#define	DDL_RCM_APB_RESET_DAC1 RCM_APBRST_DAC1RST
#define	DDL_RCM_APB_RESET_DAC2 RCM_APBRST_DAC2RST
#define	DDL_RCM_APB_RESET_COMP RCM_APBRST_COMPRST
#define	DDL_RCM_AHB_PERIPHERAL_DMA RCM_AHBCG_DMACEN
#define	DDL_RCM_AHB_PERIPHERAL_GPIO RCM_AHBCG_GPIOCEN
#define	DDL_RCM_AHB_PERIPHERAL_ADC1 RCM_AHBCG_ADC1EN
#define	DDL_RCM_AHB_PERIPHERAL_ADC2 RCM_AHBCG_ADC2EN
#define	DDL_RCM_AHB_PERIPHERAL_ADC3 RCM_AHBCG_ADC3EN
#define	DDL_RCM_AHB_PERIPHERAL_FLASH RCM_AHBCG_FLASHCEN
#define	DDL_RCM_AHB_PERIPHERAL_ROM RCM_AHBCG_ROMCEN
#define	DDL_RCM_APB_PERIPHERAL_TMR1 RCM_APBCG_TMR1CEN
#define	DDL_RCM_APB_PERIPHERAL_TMR2 RCM_APBCG_TMR2CEN
#define	DDL_RCM_APB_PERIPHERAL_TMR3 RCM_APBCG_TMR3CEN
#define	DDL_RCM_APB_PERIPHERAL_TMR4 RCM_APBCG_TMR4CEN
#define	DDL_RCM_APB_PERIPHERAL_SPI RCM_APBCG_SPICEN
#define	DDL_RCM_APB_PERIPHERAL_USART1 RCM_APBCG_USART1CEN
#define	DDL_RCM_APB_PERIPHERAL_USART2 RCM_APBCG_USART2CEN
#define	DDL_RCM_APB_PERIPHERAL_I2C RCM_APBCG_I2CCEN
#define	DDL_RCM_APB_PERIPHERAL_WWDT RCM_APBCG_WWDTCEN
#define	DDL_RCM_APB_PERIPHERAL_TS RCM_APBCG_TSCEN
#define	DDL_RCM_APB_PERIPHERAL_EINT RCM_APBCG_EINTCEN
#define	DDL_RCM_APB_PERIPHERAL_DAC1 RCM_APBCG_DAC1CEN
#define	DDL_RCM_APB_PERIPHERAL_DAC2 RCM_APBCG_DAC2CEN
#define	DDL_RCM_APB_PERIPHERAL_COMP RCM_APBCG_COMPCEN
#define	DDL_RCM_APB_PERIPHERAL_BKP RCM_APBCG_BKPCEN
#define	DDL_RCM_MCOSOURCE_SYSCLK (0x00000000U)
#define	DDL_RCM_MCOSOURCE_HSI (RCM_SCCR_CLKOUTSEL_0)
#define	DDL_RCM_MCOSOURCE_HSE (RCM_SCCR_CLKOUTSEL_1)
#define	DDL_RCM_MCOSOURCE_PLL (RCM_SCCR_CLKOUTSEL_1 \| RCM_SCCR_CLKOUTSEL_0)
#define	DDL_RCM_MCOSOURCE_LSI (RCM_SCCR_CLKOUTSEL_2)
#define	DDL_RCM_MCOSOURCE_LSE (RCM_SCCR_CLKOUTSEL_2 \| RCM_SCCR_CLKOUTSEL_0)
#define	DDL_RCM_MCO_DIV_1 (0x00000000U)
#define	DDL_RCM_MCO_DIV_2 (RCM_SCCR_CLKOUTDIV_0)
#define	DDL_RCM_MCO_DIV_4 (RCM_SCCR_CLKOUTDIV_1)
#define	DDL_RCM_MCO_DIV_8 (RCM_SCCR_CLKOUTDIV_1 \| RCM_SCCR_CLKOUTDIV_0)
#define	DDL_RCM_MCO_DIV_16 (RCM_SCCR_CLKOUTDIV_2)
#define	DDL_RCM_PLL_CLKSOURCE_NONE (0x00000000UL)
#define	DDL_RCM_PLL_CLKSOURCE_HSI (RCM_PLLCR_PLLSRC_1)
#define	DDL_RCM_PLL_CLKSOURCE_HSE (RCM_PLLCR_PLLSRC)
#define	DDL_RCM_PLL_DIV1 (0x00000000U)
#define	DDL_RCM_PLL_DIV2 (RCM_PLLCR_PLLP_1)
#define	DDL_RCM_PLL_DIV3 (RCM_PLLCR_PLLP_1 \| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV4 (RCM_PLLCR_PLLP_2)
#define	DDL_RCM_PLL_DIV5 (RCM_PLLCR_PLLP_2 \| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV6 (RCM_PLLCR_PLLP_2 \| RCM_PLLCR_PLLP_1)
#define	DDL_RCM_PLL_DIV7 (RCM_PLLCR_PLLP_2 \| RCM_PLLCR_PLLP_1 \| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV8 (RCM_PLLCR_PLLP_3)
#define	DDL_RCM_PLL_DIV9 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV10 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_1)
#define	DDL_RCM_PLL_DIV11 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_1\| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV12 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_2 )
#define	DDL_RCM_PLL_DIV13 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_2 \| RCM_PLLCR_PLLP_0)
#define	DDL_RCM_PLL_DIV14 (RCM_PLLCR_PLLP_3 \| RCM_PLLCR_PLLP_2 \| RCM_PLLCR_PLLP_1)
#define	DDL_RCM_PLL_DIV15 (RCM_PLLCR_PLLP)
#define	DDL_RCM_PERIPH_FREQUENCY_NO 0x00000000U
#define	DDL_RCM_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define	DDL_RCM_LOWPOWER_STOP (0x00000000U)
#define	DDL_RCM_LOWPOWER_STANDBY RCM_PWRCR_LPM
#define	DDL_RCM_LOWPOWER_SRAM_NO_RESET (0x00000000U)
#define	DDL_RCM_LOWPOWER_SRAM_RESET RCM_PWRCR_RAM1RET
#define	DDL_RCM_ADC16ACLK_DIV_6 (0x00000000U)
#define	DDL_RCM_ADC16ACLK_DIV_12 (RCM_ADCCR_ADC16ADIV_1)
#define	DDL_RCM_ADC16ACLK_DIV_24 (RCM_ADCCR_ADC16ADIV)
#define	DDL_RCM_ADC12ACLK_DIV_4 (0x00000000U)
#define	DDL_RCM_ADC12ACLK_DIV_8 (RCM_ADCCR_ADC12ADIV_0)
#define	DDL_RCM_ADC12ACLK_DIV_16 (RCM_ADCCR_ADC12ADIV_1)
#define	DDL_RCM_ADC12ACLK_DIV_32 (RCM_ADCCR_ADC12ADIV)
#define	DDL_RCM_ADCACLK_PLL (0x00000000U)
#define	DDL_RCM_ADCACLK_SYSCLK (RCM_ADCCR_ADCACLKSEL)
#define	DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_NONE (0x00000000UL)
#define	DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_FBK (0x00000001UL)
#define	DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_FBK_DIV2 (0x00000002UL)
#define	DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_CLKREF (0x00000003UL)
#define	DDL_RCM_LSE_DRIVE_LOW (0x00000000UL)
#define	DDL_RCM_LSE_DRIVE_HIGH RCM_SYS_ANACR0_LSEDRV
#define	DDL_RCM_WriteReg(__REG__, __VALUE__)
	Write a value in RCM register.
#define	DDL_RCM_ReadReg(__REG__)
	Read a value in RCM register.
#define	__DDL_RCM_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLP__, __PLLMUL__)
	Helper macro to calculate the PLLCLK frequency on system domain.
#define	__DDL_RCM_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__)
	Helper macro to calculate the HCLK frequency.
#define	__DDL_RCM_CALC_PCLK_FREQ(__HCLKFREQ__, __APBPRESCALER__)
	Helper macro to calculate the PCLK frequency (ABP).
#define	__DDL_RCM_KEY 0x87E4
#define	IS_DDL_RCM_LSE_DRIVE(__VALUE__)

Functions
__STATIC_INLINE void	DDL_RCM_Unlock (void)
	Unlock the RCM register.
__STATIC_INLINE void	DDL_RCM_Lock (void)
	Lock the RCM register.
__STATIC_INLINE void	DDL_RCM_EnableLSELeakageDetect (void)
	Enable LSE leakage detection.
__STATIC_INLINE void	DDL_RCM_DisableLSELeakageDetect (void)
	Disable LSE leakage detection.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledLSELeakageDetect (void)
	Check whether LSE leakage detection is enabled.
__STATIC_INLINE void	DDL_RCM_SetLSEDrive (uint32_t Drive)
	Set LSE drive capacity.
__STATIC_INLINE uint32_t	DDL_RCM_GetLSEDrive (void)
	Get LSE drive capacity.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_LSELeakageDetect (void)
	Get LSE leakage detection status.
__STATIC_INLINE void	DDL_RCM_RequestLSEAutoTrim (void)
	Request LSE leakage compensation automatic calibration.
__STATIC_INLINE void	DDL_RCM_SetLSELeakageTrim (uint32_t Trim)
	Set XIN port leakage compensation trim value.
__STATIC_INLINE uint32_t	DDL_RCM_GetLSELeakageTrim (void)
	Get XIN port leakage compensation trim value.
__STATIC_INLINE void	DDL_RCM_LSI_Enable (void)
	Enable LSI oscillator.
__STATIC_INLINE void	DDL_RCM_LSI_Disable (void)
	Disable LSI oscillator.
__STATIC_INLINE uint32_t	DDL_RCM_LSI_IsReady (void)
	Check if LSI clock is ready.
__STATIC_INLINE void	DDL_RCM_HSI_Enable (void)
	Enable HSI oscillator.
__STATIC_INLINE void	DDL_RCM_HSI_Disable (void)
	Disable HSI oscillator.
__STATIC_INLINE uint32_t	DDL_RCM_HSI_IsReady (void)
	Check if HSI clock is ready.
__STATIC_INLINE void	DDL_RCM_HSE_EnableCSS (void)
	Enable the Clock Security System.
__STATIC_INLINE void	DDL_RCM_HSE_DisableCSS (void)
	Disable the Clock Security System.
__STATIC_INLINE void	DDL_RCM_HSE_Enable (void)
	Enable HSE crystal oscillator (HSE ON).
__STATIC_INLINE void	DDL_RCM_HSE_Disable (void)
	Disable HSE crystal oscillator (HSE ON).
__STATIC_INLINE uint32_t	DDL_RCM_HSE_IsReady (void)
	Check if HSE oscillator ready.
__STATIC_INLINE uint32_t	DDL_RCM_HSE_IsByPass (void)
	Check if HSE oscillator byPass.
__STATIC_INLINE void	DDL_RCM_LSE_EnableCSS (void)
	Enable the Clock Security System.
__STATIC_INLINE void	DDL_RCM_LSE_DisableCSS (void)
	Disable the Clock Security System.
__STATIC_INLINE void	DDL_RCM_LSE_Enable (void)
	Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void	DDL_RCM_LSE_Disable (void)
	Disable Low Speed External (LSE) crystal.
__STATIC_INLINE uint32_t	DDL_RCM_LSE_IsReady (void)
	Check if LSE oscillator ready.
__STATIC_INLINE uint32_t	DDL_RCM_LSE_IsByPass (void)
	Check if LSE oscillator byPass.
__STATIC_INLINE void	DDL_RCM_PLL_Enable (void)
	Enable PLL Oscillator.
__STATIC_INLINE void	DDL_RCM_PLL_Disable (void)
	Disable PLL Oscillator.
__STATIC_INLINE uint32_t	DDL_RCM_PLL_IsReady (void)
	Check if PLL is Ready.
__STATIC_INLINE void	DDL_RCM_PLL_SetClkSource (uint32_t Source)
	Configure PLL clock source.
__STATIC_INLINE uint32_t	DDL_RCM_PLL_GetClkSource (void)
	Get PLL control clock source.
__STATIC_INLINE void	DDL_RCM_PLL_SetPrescaler (uint32_t Prescaler)
	Configure PLL clock source prescaler factor.
__STATIC_INLINE uint32_t	DDL_RCM_PLL_GetPrescaler (void)
	Get PLL clock source prescaler factor.
__STATIC_INLINE void	DDL_RCM_PLL_SetMultiplier (uint32_t Mul)
	Configure PLL multiplier.
__STATIC_INLINE uint32_t	DDL_RCM_PLL_GetMultiplier (void)
	Get PLL multiplier.
__STATIC_INLINE void	DDL_RCM_EnableBackupDomainReset (void)
	Enable backup domain reset.
__STATIC_INLINE void	DDL_RCM_DisableBackupDomainReset (void)
	Disable backup domain reset.
__STATIC_INLINE void	DDL_RCM_EnableInternalResetPulseToNRST (void)
	Enable NRST output pulse to NRST pin.
__STATIC_INLINE void	DDL_RCM_DisableInternalResetPulseToNRST (void)
	Disable NRST output pulse to NRST pin.
__STATIC_INLINE void	DDL_RCM_SetSysClkSource (uint32_t Source)
	Configure System clock source.
__STATIC_INLINE uint32_t	DDL_RCM_GetSysClkSource (void)
	Get System clock source.
__STATIC_INLINE void	DDL_RCM_EnableSysClkSwitch (void)
	Enable System clock source switching.
__STATIC_INLINE void	DDL_RCM_DisableSysClkSwitch (void)
	Disable System clock source switching.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_SWDONE (void)
	Check if swtich done event occurred or not.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_SWERR (void)
	Check if switch error event occurred or not.
__STATIC_INLINE void	DDL_RCM_SetAHBPrescaler (uint32_t Prescaler)
	Set AHB prescaler.
__STATIC_INLINE uint32_t	DDL_RCM_GetAHBPrescaler (void)
	Get AHB prescaler.
__STATIC_INLINE void	DDL_RCM_SetAPBPrescaler (uint32_t Prescaler)
	Set APB prescaler.
__STATIC_INLINE uint32_t	DDL_RCM_GetAPBPrescaler (void)
	Get APB prescaler.
__STATIC_INLINE void	DDL_RCM_EnableMCO (void)
	Enable clock output.
__STATIC_INLINE void	DDL_RCM_DisableMCO (void)
	Disable clock output.
__STATIC_INLINE void	DDL_RCM_ConfigMCO (uint32_t Source, uint32_t Prescaler)
	Configure MCOx.
__STATIC_INLINE void	DDL_RCM_EnableAHBReset (uint32_t Peripheral)
	Enable the AHB peripheral reset.
__STATIC_INLINE void	DDL_RCM_DisableAHBReset (uint32_t Peripheral)
	Disable the AHB peripheral reset.
__STATIC_INLINE void	DDL_RCM_EnableAPBReset (uint32_t Peripheral)
	Enable the APB peripheral reset.
__STATIC_INLINE void	DDL_RCM_DisableAPBReset (uint32_t Peripheral)
	Disable the APB peripheral reset.
__STATIC_INLINE void	DDL_RCM_EnableAHBPeripheral (uint32_t Peripheral)
	Enable the AHB peripheral.
__STATIC_INLINE void	DDL_RCM_DisableAHBPeripheral (uint32_t Peripheral)
	Disable the AHB peripheral.
__STATIC_INLINE void	DDL_RCM_EnableAPBPeripheral (uint32_t Peripheral)
	Enable the APB peripheral.
__STATIC_INLINE void	DDL_RCM_DisableAPBPeripheral (uint32_t Peripheral)
	Disable the APB peripheral.
__STATIC_INLINE void	DDL_RCM_SetLowPowerMode (uint32_t Mode)
	Select the low power mode when enter deep sleep mode.
__STATIC_INLINE void	DDL_RCM_SetSRAMLowPowerMode (uint32_t WorkMode)
	Configura the SRAM work mode when enter stop mode.
__STATIC_INLINE void	DDL_RCM_EnableBackupWriteProtect (void)
	Enable the back up area write protect.
__STATIC_INLINE void	DDL_RCM_DisableBackupWriteProtect (void)
	Disable the back up area write protect.
__STATIC_INLINE void	DDL_RCM_ADC_SetAdc16AnalogClkDivision (uint32_t Division)
	Set Adc16 analog clock division.
__STATIC_INLINE uint32_t	DDL_RCM_ADC_GetAdc16AnalogClkDivision (void)
	Get Adc16 analog clock division.
__STATIC_INLINE uint32_t	DDL_RCM_ADC_IsAdc16AnalogClkRDY (void)
	Check whether Adc16 analog clock is ready.
__STATIC_INLINE void	DDL_RCM_ADC_SetAdc12AnalogClkDivision (uint32_t Division)
	Set Adc12 analog clock division.
__STATIC_INLINE uint32_t	DDL_RCM_ADC_GetAdc12AnalogClkDivision (void)
	Get Adc12 analog clock division.
__STATIC_INLINE uint32_t	DDL_RCM_ADC_IsAdc12AnalogClkRDY (void)
	Check whether Adc12 analog clock is ready.
__STATIC_INLINE void	DDL_RCM_ADC_SetAdcAnalogClkSource (uint32_t Source)
	Set Adc analog clock source.
__STATIC_INLINE uint32_t	DDL_RCM_ADC_GetAdcAnalogClkSource (void)
	Get Adc analog clock source.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_LSIRDY (void)
	Check if LSI ready interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_LSIRDY (void)
	Clear LSI ready interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_LSERDY (void)
	Check if LSE ready interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_LSERDY (void)
	Clear LSE ready interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_HSIRDY (void)
	Check if HSI ready interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_HSIRDY (void)
	Clear HSI ready interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_HSERDY (void)
	Check if HSE ready interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_HSERDY (void)
	Clear HSE ready interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_PLLRDY (void)
	Check if PLL ready interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_PLLRDY (void)
	Clear PLL ready interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_HSECSS (void)
	Check if HSE clock security system interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_HSECSS (void)
	Clear HSE clock security system interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_LSECSS (void)
	Check if LSE clock security system interrupt occurred or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_LSECSS (void)
	Clear LSE clock security system interrupt flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_OPRST (void)
	Check if opload reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_OPRST (void)
	Clear opload reset flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_PINRST (void)
	Check if pin reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_PINRST (void)
	Clear pin reset flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_PORRST (void)
	Check if Borrst reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_PORRST (void)
	Clear Borrst reset flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_SFTRST (void)
	Check if Software reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_SFTRST (void)
	Clear Software reset flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_IWDTRST (void)
	Check if Independent Watchdog reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_IWDTRST (void)
	Clear if Independent Watchdog reset flag.
__STATIC_INLINE uint32_t	DDL_RCM_IsActiveFlag_WWDTRST (void)
	Check if Window Watchdog reset flag is set or not.
__STATIC_INLINE void	DDL_RCM_ClearFlag_WWDTRST (void)
	Clear Window Watchdog reset flag.
__STATIC_INLINE void	DDL_RCM_EnableIT_LSIRDY (void)
	Enable LSI ready interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_LSIRDY (void)
	Disable LSI ready interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_LSIRDY (void)
	Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_LSERDY (void)
	Enable LSE ready interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_LSERDY (void)
	Disable LSE ready interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_LSERDY (void)
	Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_HSIRDY (void)
	Enable HSI ready interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_HSIRDY (void)
	Disable HSI ready interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_HSIRDY (void)
	Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_HSERDY (void)
	Enable HSE ready interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_HSERDY (void)
	Disable HSE ready interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_HSERDY (void)
	Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_PLLRDY (void)
	Enable PLL ready interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_PLLRDY (void)
	Disable PLL ready interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_PLLRDY (void)
	Checks if PLL ready interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_HSECSS (void)
	Enable HSE clock security system interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_HSECSS (void)
	Disable HSE clock security system interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_HSECSS (void)
	Checks if HSE clock security system interrupt source is enabled or disabled.
__STATIC_INLINE void	DDL_RCM_EnableIT_LSECSS (void)
	Enable LSE clock security system interrupt.
__STATIC_INLINE void	DDL_RCM_DisableIT_LSECSS (void)
	Disable LSE clock security system interrupt.
__STATIC_INLINE uint32_t	DDL_RCM_IsEnabledIT_LSECSS (void)
	Checks if LSE clock security system interrupt source is enabled or disabled.
ErrorStatus	DDL_RCM_DeInit (void)
	Reset the RCM clock configuration to the default reset state.
void	DDL_RCM_GetSystemClocksFreq (DDL_RCM_ClocksTypeDef *RCM_Clocks)
	Return the frequencies of different on chip clocks; System, AHB, APB buses clocks.

Variables
const uint8_t	AHBPrescTable [16]
const uint8_t	APBPrescTable [8]

Detailed Description

Header file of RCM DDL module.

Attention

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The original code has been modified by Geehy Semiconductor.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file g32r4xx_ddl_rcm.h.

Data Structures

Macros

Functions

Variables

Detailed Description