g32r4xx_ddl_rcm.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_RCM_H
#define G32R4xx_DDL_RCM_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined(RCM)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)
extern const uint8_t  AHBPrescTable[16];  
extern const uint8_t  APBPrescTable[8];   
#endif /*USE_FULL_DDL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)


typedef struct
{
  uint32_t SYSCLK_Frequency;  
  uint32_t HCLK_Frequency;    
  uint32_t PCLK_Frequency;    
} DDL_RCM_ClocksTypeDef;


#endif /* USE_FULL_DDL_DRIVER */
 
/* Exported constants --------------------------------------------------------*/

#if !defined  (HSE_VALUE)
#define HSE_VALUE  8000000U  
#endif /* HSE_VALUE */
 
#if !defined  (HSI_VALUE)
#define HSI_VALUE  8000000U  
#endif /* HSI_VALUE */
 
#if !defined  (LSE_VALUE)
#define LSE_VALUE  32768U  
#endif /* LSE_VALUE */
 
#if !defined  (LSI_VALUE)
#define LSI_VALUE  32000U  
#endif /* LSI_VALUE */

#define DDL_RCM_INT_LSIRDYFLG      RCM_CICR_LSIRDYF     
#define DDL_RCM_INT_LSERDYFLG      RCM_CICR_LSERDYF     
#define DDL_RCM_INT_HSIRDYFLG      RCM_CICR_HSIRDYF     
#define DDL_RCM_INT_HSERDYFLG      RCM_CICR_HSERDYF     
#define DDL_RCM_INT_PLLRDYFLG      RCM_CICR_PLLRDYF     
#define DDL_RCM_INT_HSECSSFLG      RCM_CICR_HSECSSF     
#define DDL_RCM_INT_LSECSSFLG      RCM_CICR_LSECSSF     
#define DDL_RCM_RSTCSR_OPRSTFLG    RCM_RSTCSR_OPRSTF    
#define DDL_RCM_RSTCSR_PINRSTFLG   RCM_RSTCSR_PINRSTF   
#define DDL_RCM_RSTCSR_PORRSTFLG   RCM_RSTCSR_PORRSTF   
#define DDL_RCM_RSTCSR_SFTRSTFLG   RCM_RSTCSR_SFTRSTF   
#define DDL_RCM_RSTCSR_IWDTRSTFLG  RCM_RSTCSR_IWDTRSTF  
#define DDL_RCM_RSTCSR_WWDTRSTFLG  RCM_RSTCSR_WWDTRSTF  

#define DDL_RCM_INT_LSIRDYEN  RCM_CIER_LSIRDYIE  
#define DDL_RCM_INT_LSERDYEN  RCM_CIER_LSERDYIE  
#define DDL_RCM_INT_HSIRDYEN  RCM_CIER_HSIRDYIE  
#define DDL_RCM_INT_HSERDYEN  RCM_CIER_HSERDYIE  
#define DDL_RCM_INT_PLLRDYEN  RCM_CIER_PLLRDYIE  
#define DDL_RCM_INT_HSECSSEN  RCM_CIER_HSECSSIE  
#define DDL_RCM_INT_LSECSSEN  RCM_CIER_LSECSSIE  

#define DDL_RCM_SYS_CLKSOURCE_HSI  (0x00000000U)  
#define DDL_RCM_SYS_CLKSOURCE_HSE  (0x00000001U)  
#define DDL_RCM_SYS_CLKSOURCE_PLL  (0x00000002U)  

#define DDL_RCM_AHB_DIV_1    (RCM_SCCR_HDIV_0)                                      
#define DDL_RCM_AHB_DIV_2    (RCM_SCCR_HDIV_3)                                      
#define DDL_RCM_AHB_DIV_4    (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_0)                    
#define DDL_RCM_AHB_DIV_8    (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_1)                    
#define DDL_RCM_AHB_DIV_16   (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_1 | RCM_SCCR_HDIV_0)  
#define DDL_RCM_AHB_DIV_32   (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_2)                    
#define DDL_RCM_AHB_DIV_64   (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_2 | RCM_SCCR_HDIV_0)  
#define DDL_RCM_AHB_DIV_128  (RCM_SCCR_HDIV_3 | RCM_SCCR_HDIV_2 | RCM_SCCR_HDIV_1)  
#define DDL_RCM_AHB_DIV_256  (RCM_SCCR_HDIV)                                        

#define DDL_RCM_APB_DIV_1   (0x00000000U)                        
#define DDL_RCM_APB_DIV_2   (RCM_SCCR_PDIV_2)                    
#define DDL_RCM_APB_DIV_4   (RCM_SCCR_PDIV_2 | RCM_SCCR_PDIV_0)  
#define DDL_RCM_APB_DIV_8   (RCM_SCCR_PDIV_2 | RCM_SCCR_PDIV_1)  
#define DDL_RCM_APB_DIV_16  (RCM_SCCR_PDIV)                      

#define DDL_RCM_AHB_RESET_DMA    RCM_AHBRST_DMARST
#define DDL_RCM_AHB_RESET_GPIO   RCM_AHBRST_GPIORST
#define DDL_RCM_AHB_RESET_ADC1   RCM_AHBRST_ADC1RST
#define DDL_RCM_AHB_RESET_ADC2   RCM_AHBRST_ADC2RST
#define DDL_RCM_AHB_RESET_ADC3   RCM_AHBRST_ADC3RST
#define DDL_RCM_AHB_RESET_FLASH  RCM_AHBRST_FLASHRST

#define DDL_RCM_APB_RESET_TMR1    RCM_APBRST_TMR1RST
#define DDL_RCM_APB_RESET_TMR2    RCM_APBRST_TMR2RST
#define DDL_RCM_APB_RESET_TMR3    RCM_APBRST_TMR3RST
#define DDL_RCM_APB_RESET_TMR4    RCM_APBRST_TMR4RST
#define DDL_RCM_APB_RESET_SPI     RCM_APBRST_SPIRST
#define DDL_RCM_APB_RESET_USART1  RCM_APBRST_USART1RST
#define DDL_RCM_APB_RESET_USART2  RCM_APBRST_USART2RST
#define DDL_RCM_APB_RESET_I2C     RCM_APBRST_I2CRST
#define DDL_RCM_APB_RESET_TS      RCM_APBRST_TSRST
#define DDL_RCM_APB_RESET_EINT    RCM_APBRST_EINTRST
#define DDL_RCM_APB_RESET_DAC1    RCM_APBRST_DAC1RST
#define DDL_RCM_APB_RESET_DAC2    RCM_APBRST_DAC2RST
#define DDL_RCM_APB_RESET_COMP    RCM_APBRST_COMPRST

#define DDL_RCM_AHB_PERIPHERAL_DMA    RCM_AHBCG_DMACEN
#define DDL_RCM_AHB_PERIPHERAL_GPIO   RCM_AHBCG_GPIOCEN
#define DDL_RCM_AHB_PERIPHERAL_ADC1   RCM_AHBCG_ADC1EN
#define DDL_RCM_AHB_PERIPHERAL_ADC2   RCM_AHBCG_ADC2EN
#define DDL_RCM_AHB_PERIPHERAL_ADC3   RCM_AHBCG_ADC3EN
#define DDL_RCM_AHB_PERIPHERAL_FLASH  RCM_AHBCG_FLASHCEN
#define DDL_RCM_AHB_PERIPHERAL_ROM    RCM_AHBCG_ROMCEN

#define DDL_RCM_APB_PERIPHERAL_TMR1    RCM_APBCG_TMR1CEN
#define DDL_RCM_APB_PERIPHERAL_TMR2    RCM_APBCG_TMR2CEN
#define DDL_RCM_APB_PERIPHERAL_TMR3    RCM_APBCG_TMR3CEN
#define DDL_RCM_APB_PERIPHERAL_TMR4    RCM_APBCG_TMR4CEN
#define DDL_RCM_APB_PERIPHERAL_SPI     RCM_APBCG_SPICEN
#define DDL_RCM_APB_PERIPHERAL_USART1  RCM_APBCG_USART1CEN
#define DDL_RCM_APB_PERIPHERAL_USART2  RCM_APBCG_USART2CEN
#define DDL_RCM_APB_PERIPHERAL_I2C     RCM_APBCG_I2CCEN
#define DDL_RCM_APB_PERIPHERAL_WWDT    RCM_APBCG_WWDTCEN
#define DDL_RCM_APB_PERIPHERAL_TS      RCM_APBCG_TSCEN
#define DDL_RCM_APB_PERIPHERAL_EINT    RCM_APBCG_EINTCEN
#define DDL_RCM_APB_PERIPHERAL_DAC1    RCM_APBCG_DAC1CEN
#define DDL_RCM_APB_PERIPHERAL_DAC2    RCM_APBCG_DAC2CEN
#define DDL_RCM_APB_PERIPHERAL_COMP    RCM_APBCG_COMPCEN
#define DDL_RCM_APB_PERIPHERAL_BKP     RCM_APBCG_BKPCEN

#define DDL_RCM_MCOSOURCE_SYSCLK  (0x00000000U)                                  
#define DDL_RCM_MCOSOURCE_HSI     (RCM_SCCR_CLKOUTSEL_0)                         
#define DDL_RCM_MCOSOURCE_HSE     (RCM_SCCR_CLKOUTSEL_1)                         
#define DDL_RCM_MCOSOURCE_PLL     (RCM_SCCR_CLKOUTSEL_1 | RCM_SCCR_CLKOUTSEL_0)  
#define DDL_RCM_MCOSOURCE_LSI     (RCM_SCCR_CLKOUTSEL_2)                         
#define DDL_RCM_MCOSOURCE_LSE     (RCM_SCCR_CLKOUTSEL_2 | RCM_SCCR_CLKOUTSEL_0)  

#define DDL_RCM_MCO_DIV_1   (0x00000000U)                                  
#define DDL_RCM_MCO_DIV_2   (RCM_SCCR_CLKOUTDIV_0)                         
#define DDL_RCM_MCO_DIV_4   (RCM_SCCR_CLKOUTDIV_1)                         
#define DDL_RCM_MCO_DIV_8   (RCM_SCCR_CLKOUTDIV_1 | RCM_SCCR_CLKOUTDIV_0)  
#define DDL_RCM_MCO_DIV_16  (RCM_SCCR_CLKOUTDIV_2)                         

#define DDL_RCM_PLL_CLKSOURCE_NONE  (0x00000000UL)        
#define DDL_RCM_PLL_CLKSOURCE_HSI   (RCM_PLLCR_PLLSRC_1)  
#define DDL_RCM_PLL_CLKSOURCE_HSE   (RCM_PLLCR_PLLSRC)    

#define DDL_RCM_PLL_DIV1   (0x00000000U)                                             
#define DDL_RCM_PLL_DIV2   (RCM_PLLCR_PLLP_1)                                        
#define DDL_RCM_PLL_DIV3   (RCM_PLLCR_PLLP_1 | RCM_PLLCR_PLLP_0)                     
#define DDL_RCM_PLL_DIV4   (RCM_PLLCR_PLLP_2)                                        
#define DDL_RCM_PLL_DIV5   (RCM_PLLCR_PLLP_2 | RCM_PLLCR_PLLP_0)                     
#define DDL_RCM_PLL_DIV6   (RCM_PLLCR_PLLP_2 | RCM_PLLCR_PLLP_1)                     
#define DDL_RCM_PLL_DIV7   (RCM_PLLCR_PLLP_2 | RCM_PLLCR_PLLP_1 | RCM_PLLCR_PLLP_0)  
#define DDL_RCM_PLL_DIV8   (RCM_PLLCR_PLLP_3)                                        
#define DDL_RCM_PLL_DIV9   (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_0)                     
#define DDL_RCM_PLL_DIV10  (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_1)                     
#define DDL_RCM_PLL_DIV11  (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_1| RCM_PLLCR_PLLP_0)   
#define DDL_RCM_PLL_DIV12  (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_2 )                    
#define DDL_RCM_PLL_DIV13  (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_2 | RCM_PLLCR_PLLP_0)  
#define DDL_RCM_PLL_DIV14  (RCM_PLLCR_PLLP_3 | RCM_PLLCR_PLLP_2 | RCM_PLLCR_PLLP_1)  
#define DDL_RCM_PLL_DIV15  (RCM_PLLCR_PLLP)                                          
 
#if defined(USE_FULL_DDL_DRIVER)
#define DDL_RCM_PERIPH_FREQUENCY_NO  0x00000000U  
#define DDL_RCM_PERIPH_FREQUENCY_NA  0xFFFFFFFFU  
#endif /* USE_FULL_DDL_DRIVER */

#define DDL_RCM_LOWPOWER_STOP           (0x00000000U)
#define DDL_RCM_LOWPOWER_STANDBY        RCM_PWRCR_LPM
#define DDL_RCM_LOWPOWER_SRAM_NO_RESET  (0x00000000U)
#define DDL_RCM_LOWPOWER_SRAM_RESET     RCM_PWRCR_RAM1RET

#define DDL_RCM_ADC16ACLK_DIV_6   (0x00000000U)
#define DDL_RCM_ADC16ACLK_DIV_12  (RCM_ADCCR_ADC16ADIV_1)
#define DDL_RCM_ADC16ACLK_DIV_24  (RCM_ADCCR_ADC16ADIV)

#define DDL_RCM_ADC12ACLK_DIV_4   (0x00000000U)
#define DDL_RCM_ADC12ACLK_DIV_8   (RCM_ADCCR_ADC12ADIV_0)
#define DDL_RCM_ADC12ACLK_DIV_16  (RCM_ADCCR_ADC12ADIV_1)
#define DDL_RCM_ADC12ACLK_DIV_32  (RCM_ADCCR_ADC12ADIV)

#define DDL_RCM_ADCACLK_PLL     (0x00000000U)
#define DDL_RCM_ADCACLK_SYSCLK  (RCM_ADCCR_ADCACLKSEL)

#define DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_NONE      (0x00000000UL)
#define DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_FBK       (0x00000001UL)
#define DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_FBK_DIV2  (0x00000002UL)
#define DDL_RCM_PLL_INTERCLK_OUTPUTSOURCE_CLKREF    (0x00000003UL)

#define DDL_RCM_LSE_DRIVE_LOW   (0x00000000UL)
#define DDL_RCM_LSE_DRIVE_HIGH  RCM_SYS_ANACR0_LSEDRV

 
/* Exported macro ------------------------------------------------------------*/


#define DDL_RCM_WriteReg(__REG__,  __VALUE__) WRITE_REG(RCM->__REG__, (__VALUE__))

#define DDL_RCM_ReadReg(__REG__)  READ_REG(RCM->__REG__)


#define __DDL_RCM_CALC_PLLCLK_FREQ(__INPUTFREQ__,  __PLLP__, __PLLMUL__) (((__INPUTFREQ__) / (__PLLP__)) * (__PLLMUL__))

#define __DDL_RCM_CALC_HCLK_FREQ(__SYSCLKFREQ__,   __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCM_SCCR_HDIV) >>  RCM_SCCR_HDIV_Pos])

#define __DDL_RCM_CALC_PCLK_FREQ(__HCLKFREQ__,     __APBPRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APBPRESCALER__) >>  RCM_SCCR_PDIV_Pos])
 
#define __DDL_RCM_KEY                              0x87E4
 
#define IS_DDL_RCM_LSE_DRIVE(__VALUE__)  (((__VALUE__) == DDL_RCM_LSE_DRIVE_LOW) \
                                      || ((__VALUE__) == DDL_RCM_LSE_DRIVE_HIGH))


 
/* Exported functions --------------------------------------------------------*/


__STATIC_INLINE void DDL_RCM_Unlock(void)
{
  WRITE_REG(RCM->KEY, (0xffff & __DDL_RCM_KEY));
}

__STATIC_INLINE void DDL_RCM_Lock(void)
{
  SET_BIT(RCM->KEY, RCM_KEY_KEYST);
}



__STATIC_INLINE void DDL_RCM_EnableLSELeakageDetect(void)
{
  SET_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSELKDTEN);
}

__STATIC_INLINE void DDL_RCM_DisableLSELeakageDetect(void)
{
  CLEAR_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSELKDTEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledLSELeakageDetect(void)
{
  return ((READ_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSELKDTEN) == RCM_SYS_ANACR0_LSELKDTEN) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_RCM_SetLSEDrive(uint32_t Drive)
{
  MODIFY_REG(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSEDRV, Drive);
}

__STATIC_INLINE uint32_t DDL_RCM_GetLSEDrive(void)
{
  return (uint32_t)READ_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSEDRV);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_LSELeakageDetect(void)
{
  return ((READ_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSELKDTSTA) == RCM_SYS_ANACR0_LSELKDTSTA) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_RCM_RequestLSEAutoTrim(void)
{
  SET_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSEAUTOTRIMREQ);
}

__STATIC_INLINE void DDL_RCM_SetLSELeakageTrim(uint32_t Trim)
{
  MODIFY_REG(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSE_LEAKTRIM, (Trim << RCM_SYS_ANACR0_LSE_LEAKTRIM_Pos));
}

__STATIC_INLINE uint32_t DDL_RCM_GetLSELeakageTrim(void)
{
  return (uint32_t)(READ_BIT(RCM->SYS_ANACR0, RCM_SYS_ANACR0_LSE_LEAKTRIM) >> RCM_SYS_ANACR0_LSE_LEAKTRIM_Pos);
}



__STATIC_INLINE void DDL_RCM_LSI_Enable(void)
{
  SET_BIT(PMU->CR, PMU_CR_LSION);
}

__STATIC_INLINE void DDL_RCM_LSI_Disable(void)
{
  CLEAR_BIT(PMU->CR, PMU_CR_LSION);
}

__STATIC_INLINE uint32_t DDL_RCM_LSI_IsReady(void)
{
  return (READ_BIT(PMU->CR, PMU_CR_LSIRDY) == (PMU_CR_LSIRDY));
}



__STATIC_INLINE void DDL_RCM_HSI_Enable(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_HSION);
}

__STATIC_INLINE void DDL_RCM_HSI_Disable(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_HSION);
}

__STATIC_INLINE uint32_t DDL_RCM_HSI_IsReady(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_HSIRDY) == (RCM_RCCR_HSIRDY));
}



__STATIC_INLINE void DDL_RCM_HSE_EnableCSS(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_CSSON);
}

__STATIC_INLINE void DDL_RCM_HSE_DisableCSS(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_CSSON);
}

__STATIC_INLINE void DDL_RCM_HSE_Enable(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_HSEON);
}

__STATIC_INLINE void DDL_RCM_HSE_Disable(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_HSEON);
}

__STATIC_INLINE uint32_t DDL_RCM_HSE_IsReady(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_HSERDY) == (RCM_RCCR_HSERDY));
}

__STATIC_INLINE uint32_t DDL_RCM_HSE_IsByPass(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_HSEBYPASS) == (RCM_RCCR_HSEBYPASS));
}


__STATIC_INLINE void DDL_RCM_LSE_EnableCSS(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_LSECSSON);
}

__STATIC_INLINE void DDL_RCM_LSE_DisableCSS(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_LSECSSON);
}

__STATIC_INLINE void DDL_RCM_LSE_Enable(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_LSEON);
}

__STATIC_INLINE void DDL_RCM_LSE_Disable(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_LSEON);
}

__STATIC_INLINE uint32_t DDL_RCM_LSE_IsReady(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_LSERDY) == (RCM_RCCR_LSERDY));
}

__STATIC_INLINE uint32_t DDL_RCM_LSE_IsByPass(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_LSEBYPASS) == (RCM_RCCR_LSEBYPASS));
}


__STATIC_INLINE void DDL_RCM_PLL_Enable(void)
{
  SET_BIT(RCM->RCCR, RCM_RCCR_PLLON);
}

__STATIC_INLINE void DDL_RCM_PLL_Disable(void)
{
  CLEAR_BIT(RCM->RCCR, RCM_RCCR_PLLON);
}

__STATIC_INLINE uint32_t DDL_RCM_PLL_IsReady(void)
{
  return (READ_BIT(RCM->RCCR, RCM_RCCR_PLLRDY) == (RCM_RCCR_PLLRDY));
}

__STATIC_INLINE void DDL_RCM_PLL_SetClkSource(uint32_t Source)
{
  MODIFY_REG(RCM->PLLCR, RCM_PLLCR_PLLSRC, Source);
}

__STATIC_INLINE uint32_t DDL_RCM_PLL_GetClkSource(void)
{
  return (uint32_t)(READ_BIT(RCM->PLLCR, RCM_PLLCR_PLLSRC));
}

__STATIC_INLINE void DDL_RCM_PLL_SetPrescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCM->PLLCR, RCM_PLLCR_PLLP, Prescaler);
}

__STATIC_INLINE uint32_t DDL_RCM_PLL_GetPrescaler(void)
{
  return (uint32_t)(READ_BIT(RCM->PLLCR, RCM_PLLCR_PLLP));
}

__STATIC_INLINE void DDL_RCM_PLL_SetMultiplier(uint32_t Mul)
{
  MODIFY_REG(RCM->PLLCR, RCM_PLLCR_PLLMUL, (Mul << RCM_PLLCR_PLLMUL_Pos));
}

__STATIC_INLINE uint32_t DDL_RCM_PLL_GetMultiplier(void)
{
  return (uint32_t)(READ_BIT(RCM->PLLCR, RCM_PLLCR_PLLMUL) >> RCM_PLLCR_PLLMUL_Pos);
}



__STATIC_INLINE void DDL_RCM_EnableBackupDomainReset(void)
{
  SET_BIT(PMU->CR, (uint32_t)PMU_CR_BDRST);
}

__STATIC_INLINE void DDL_RCM_DisableBackupDomainReset(void)
{
  CLEAR_BIT(PMU->CR, (uint32_t)PMU_CR_BDRST);
}



__STATIC_INLINE void DDL_RCM_EnableInternalResetPulseToNRST(void)
{
  SET_BIT(PMU->CR, (uint32_t)PMU_CR_NRSTOUTDIS);
}

__STATIC_INLINE void DDL_RCM_DisableInternalResetPulseToNRST(void)
{
  CLEAR_BIT(PMU->CR, (uint32_t)PMU_CR_NRSTOUTDIS);
}


__STATIC_INLINE void DDL_RCM_SetSysClkSource(uint32_t Source)
{
  MODIFY_REG(RCM->SCCR, RCM_SCCR_SW, (Source << RCM_SCCR_SW_Pos));
}

__STATIC_INLINE uint32_t DDL_RCM_GetSysClkSource(void)
{
  return (uint32_t)(READ_BIT(RCM->MCCR, RCM_MCCR_SWST) >> RCM_MCCR_SWST_Pos);
}

__STATIC_INLINE void DDL_RCM_EnableSysClkSwitch(void)
{
  SET_BIT(RCM->MCCR, RCM_MCCR_CSEN);
}

__STATIC_INLINE void DDL_RCM_DisableSysClkSwitch(void)
{
  CLEAR_BIT(RCM->MCCR, RCM_MCCR_CSEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_SWDONE(void)
{
  return (uint32_t)(READ_BIT(RCM->MCCR, RCM_MCCR_SWDONE) == RCM_MCCR_SWDONE ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_SWERR(void)
{
  return (uint32_t)(READ_BIT(RCM->MCCR, RCM_MCCR_SWERR) == RCM_MCCR_SWERR ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_RCM_SetAHBPrescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCM->SCCR, RCM_SCCR_HDIV, Prescaler);
}

__STATIC_INLINE uint32_t DDL_RCM_GetAHBPrescaler(void)
{
  return (uint32_t)(READ_BIT(RCM->SCCR, RCM_SCCR_HDIV));
}

__STATIC_INLINE void DDL_RCM_SetAPBPrescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCM->SCCR, RCM_SCCR_PDIV, Prescaler);
}

__STATIC_INLINE uint32_t DDL_RCM_GetAPBPrescaler(void)
{
  return (uint32_t)(READ_BIT(RCM->SCCR, RCM_SCCR_PDIV));
}


__STATIC_INLINE void DDL_RCM_EnableMCO(void)
{
  SET_BIT(RCM->SCCR, RCM_SCCR_CLKOUTEN);
}

__STATIC_INLINE void DDL_RCM_DisableMCO(void)
{
  CLEAR_BIT(RCM->SCCR, RCM_SCCR_CLKOUTEN);
}

__STATIC_INLINE void DDL_RCM_ConfigMCO(uint32_t Source, uint32_t Prescaler)
{
  MODIFY_REG(RCM->SCCR, (RCM_SCCR_CLKOUTSEL | RCM_SCCR_CLKOUTDIV),  (Source | Prescaler));
}


__STATIC_INLINE void DDL_RCM_EnableAHBReset(uint32_t Peripheral)
{
  CLEAR_BIT(RCM->AHBRST, Peripheral);
}

__STATIC_INLINE void DDL_RCM_DisableAHBReset(uint32_t Peripheral)
{
  SET_BIT(RCM->AHBRST, Peripheral);
}

__STATIC_INLINE void DDL_RCM_EnableAPBReset(uint32_t Peripheral)
{
  CLEAR_BIT(RCM->APBRST, Peripheral);
}

__STATIC_INLINE void DDL_RCM_DisableAPBReset(uint32_t Peripheral)
{
  SET_BIT(RCM->APBRST, Peripheral);
}


__STATIC_INLINE void DDL_RCM_EnableAHBPeripheral(uint32_t Peripheral)
{
  SET_BIT(RCM->AHBCG, Peripheral);
}

__STATIC_INLINE void DDL_RCM_DisableAHBPeripheral(uint32_t Peripheral)
{
  CLEAR_BIT(RCM->AHBCG, Peripheral);
}

__STATIC_INLINE void DDL_RCM_EnableAPBPeripheral(uint32_t Peripheral)
{
  SET_BIT(RCM->APBCG, Peripheral);
}

__STATIC_INLINE void DDL_RCM_DisableAPBPeripheral(uint32_t Peripheral)
{
  CLEAR_BIT(RCM->APBCG, Peripheral);
}


__STATIC_INLINE void DDL_RCM_SetLowPowerMode(uint32_t Mode)
{
  MODIFY_REG(RCM->PWRCR, RCM_PWRCR_LPM, Mode);
}

__STATIC_INLINE void DDL_RCM_SetSRAMLowPowerMode(uint32_t WorkMode)
{
  MODIFY_REG(RCM->PWRCR, RCM_PWRCR_RAM1RET, WorkMode);
}

__STATIC_INLINE void DDL_RCM_EnableBackupWriteProtect(void)
{
  CLEAR_BIT(RCM->PWRCR, RCM_PWRCR_BKPWP);
}

__STATIC_INLINE void DDL_RCM_DisableBackupWriteProtect(void)
{
  SET_BIT(RCM->PWRCR, RCM_PWRCR_BKPWP);
}



__STATIC_INLINE void DDL_RCM_ADC_SetAdc16AnalogClkDivision(uint32_t Division)
{
  MODIFY_REG(RCM->ADCCR, RCM_ADCCR_ADC16ADIV, Division);
}

__STATIC_INLINE uint32_t DDL_RCM_ADC_GetAdc16AnalogClkDivision(void)
{
  return (uint32_t)(READ_BIT(RCM->ADCCR, RCM_ADCCR_ADC16ADIV));
}

__STATIC_INLINE uint32_t DDL_RCM_ADC_IsAdc16AnalogClkRDY(void)
{
  return (uint32_t)(READ_BIT(RCM->ADCCR, RCM_ADCCR_ADC16ACLKRDY) == RCM_ADCCR_ADC16ACLKRDY);
}

__STATIC_INLINE void DDL_RCM_ADC_SetAdc12AnalogClkDivision(uint32_t Division)
{
  MODIFY_REG(RCM->ADCCR, RCM_ADCCR_ADC12ADIV, Division);
}

__STATIC_INLINE uint32_t DDL_RCM_ADC_GetAdc12AnalogClkDivision(void)
{
  return (uint32_t)(READ_BIT(RCM->ADCCR, RCM_ADCCR_ADC12ADIV));
}

__STATIC_INLINE uint32_t DDL_RCM_ADC_IsAdc12AnalogClkRDY(void)
{
  return (uint32_t)(READ_BIT(RCM->ADCCR, RCM_ADCCR_ADC12ACLKRDY) == RCM_ADCCR_ADC12ACLKRDY);
}

__STATIC_INLINE void DDL_RCM_ADC_SetAdcAnalogClkSource(uint32_t Source)
{
  MODIFY_REG(RCM->ADCCR, RCM_ADCCR_ADCACLKSEL, Source);
}

__STATIC_INLINE uint32_t DDL_RCM_ADC_GetAdcAnalogClkSource(void)
{
  return (uint32_t)(READ_BIT(RCM->ADCCR, RCM_ADCCR_ADCACLKSEL));
}


__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_LSIRDY(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_LSIRDYFLG) == (DDL_RCM_INT_LSIRDYFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_LSIRDY(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_LSIRDYFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_LSERDY(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_LSERDYFLG) == (DDL_RCM_INT_LSERDYFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_LSERDY(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_LSERDYFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_HSIRDY(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_HSIRDYFLG) == (DDL_RCM_INT_HSIRDYFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_HSIRDY(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_HSIRDYFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_HSERDY(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_HSERDYFLG) == (DDL_RCM_INT_HSERDYFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_HSERDY(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_HSERDYFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_PLLRDY(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_PLLRDYFLG) == (DDL_RCM_INT_PLLRDYFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_PLLRDY(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_PLLRDYFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_HSECSS(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_HSECSSFLG) == (DDL_RCM_INT_HSECSSFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_HSECSS(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_HSECSSFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_LSECSS(void)
{
  return (READ_BIT(RCM->CICR, DDL_RCM_INT_LSECSSFLG) == (DDL_RCM_INT_LSECSSFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_LSECSS(void)
{
  WRITE_REG(RCM->CICR, DDL_RCM_INT_LSECSSFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_OPRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_OPRSTFLG) == (DDL_RCM_RSTCSR_OPRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_OPRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_OPRSTFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_PINRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_PINRSTFLG) == (DDL_RCM_RSTCSR_PINRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_PINRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_PINRSTFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_PORRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_PORRSTFLG) == (DDL_RCM_RSTCSR_PORRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_PORRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_PORRSTFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_SFTRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_SFTRSTFLG) == (DDL_RCM_RSTCSR_SFTRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_SFTRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_SFTRSTFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_IWDTRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_IWDTRSTFLG) == (DDL_RCM_RSTCSR_IWDTRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_IWDTRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_IWDTRSTFLG);
}

__STATIC_INLINE uint32_t DDL_RCM_IsActiveFlag_WWDTRST(void)
{
  return (READ_BIT(RCM->RSTCSR, DDL_RCM_RSTCSR_WWDTRSTFLG) == (DDL_RCM_RSTCSR_WWDTRSTFLG));
}

__STATIC_INLINE void DDL_RCM_ClearFlag_WWDTRST(void)
{
  WRITE_REG(RCM->RSTCSR, DDL_RCM_RSTCSR_WWDTRSTFLG);
}


__STATIC_INLINE void DDL_RCM_EnableIT_LSIRDY(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_LSIRDYEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_LSIRDY(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_LSIRDYEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_LSIRDY(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_LSIRDYEN) == (DDL_RCM_INT_LSIRDYEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_LSERDY(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_LSERDYEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_LSERDY(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_LSERDYEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_LSERDY(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_LSERDYEN) == (DDL_RCM_INT_LSERDYEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_HSIRDY(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_HSIRDYEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_HSIRDY(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_HSIRDYEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_HSIRDY(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_HSIRDYEN) == (DDL_RCM_INT_HSIRDYEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_HSERDY(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_HSERDYEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_HSERDY(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_HSERDYEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_HSERDY(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_HSERDYEN) == (DDL_RCM_INT_HSERDYEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_PLLRDY(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_PLLRDYEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_PLLRDY(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_PLLRDYEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_PLLRDY(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_PLLRDYEN) == (DDL_RCM_INT_PLLRDYEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_HSECSS(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_HSECSSEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_HSECSS(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_HSECSSEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_HSECSS(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_HSECSSEN) == (DDL_RCM_INT_HSECSSEN));
}

__STATIC_INLINE void DDL_RCM_EnableIT_LSECSS(void)
{
  SET_BIT(RCM->CIER, DDL_RCM_INT_LSECSSEN);
}

__STATIC_INLINE void DDL_RCM_DisableIT_LSECSS(void)
{
  CLEAR_BIT(RCM->CIER, DDL_RCM_INT_LSECSSEN);
}

__STATIC_INLINE uint32_t DDL_RCM_IsEnabledIT_LSECSS(void)
{
  return (READ_BIT(RCM->CIER, DDL_RCM_INT_LSECSSEN) == (DDL_RCM_INT_LSECSSEN));
}

 
#if defined(USE_FULL_DDL_DRIVER)
ErrorStatus DDL_RCM_DeInit(void);

void        DDL_RCM_GetSystemClocksFreq(DDL_RCM_ClocksTypeDef *RCM_Clocks);
 
#endif /* USE_FULL_DDL_DRIVER */


 
#endif /* defined(RCM) */

 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4xx_DDL_RCM_H */