g32r4xx_ddl_spi.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef g32r4xx_DDL_SPI_H
#define g32r4xx_DDL_SPI_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"
#include "g32r430.h"

#if defined (SPI1)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
 
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)

typedef struct
{
  uint32_t TransferDirection;       
 
  uint32_t Mode;                    
 
  uint32_t DataWidth;               
 
  uint32_t ClockPolarity;           
 
  uint32_t ClockPhase;              
 
  uint32_t NSS;                     
 
  uint32_t BaudRate;                
 
  uint32_t BitOrder;                
 
  uint32_t CRCCalculation;          
 
  uint32_t CRCPoly;                 
 
} DDL_SPI_InitTypeDef;

#endif /* USE_FULL_DDL_DRIVER */
 
/* Exported constants --------------------------------------------------------*/

#define DDL_SPI_STS_RXBNEFLG  SPI_STS_RXBNEFLG  
#define DDL_SPI_STS_TXBEFLG   SPI_STS_TXBEFLG   
#define DDL_SPI_STS_BSYFLG    SPI_STS_BSYFLG    
#define DDL_SPI_STS_CRCEFLG   SPI_STS_CRCEFLG   
#define DDL_SPI_STS_MEFLG     SPI_STS_MEFLG     
#define DDL_SPI_STS_OVRFLG    SPI_STS_OVRFLG    
#define DDL_SPI_STS_FREFLG    SPI_STS_FREFLG    

#define DDL_SPI_CTRL2_RXBNEIEN  SPI_CTRL2_RXBNEIEN  
#define DDL_SPI_CTRL2_TXBEIEN   SPI_CTRL2_TXBEIEN   
#define DDL_SPI_CTRL2_ERRIEN    SPI_CTRL2_ERRIEN    

#define DDL_SPI_MODE_MASTER  (SPI_CTRL1_MSMCFG | SPI_CTRL1_ISSEL)  
#define DDL_SPI_MODE_SLAVE   0x00000000U                           

#define DDL_SPI_PROTOCOL_MOTOROLA  0x00000000U         
#define DDL_SPI_PROTOCOL_TI        (SPI_CTRL2_FRFCFG)  

#define DDL_SPI_PHASE_1EDGE  0x00000000U       
#define DDL_SPI_PHASE_2EDGE  (SPI_CTRL1_CPHA)  

#define DDL_SPI_POLARITY_LOW   0x00000000U       
#define DDL_SPI_POLARITY_HIGH  (SPI_CTRL1_CPOL)  

#define DDL_SPI_BAUDRATEPRESCALER_DIV2    (0x00000000U)                            
#define DDL_SPI_BAUDRATEPRESCALER_DIV4    (SPI_CTRL1_BRSEL_0)                      
#define DDL_SPI_BAUDRATEPRESCALER_DIV8    (SPI_CTRL1_BRSEL_1)                      
#define DDL_SPI_BAUDRATEPRESCALER_DIV16   (SPI_CTRL1_BRSEL_1 | SPI_CTRL1_BRSEL_0)  
#define DDL_SPI_BAUDRATEPRESCALER_DIV32   (SPI_CTRL1_BRSEL_2)                      
#define DDL_SPI_BAUDRATEPRESCALER_DIV64   (SPI_CTRL1_BRSEL_2 | SPI_CTRL1_BRSEL_0)  
#define DDL_SPI_BAUDRATEPRESCALER_DIV128  (SPI_CTRL1_BRSEL_2 | SPI_CTRL1_BRSEL_1)  
#define DDL_SPI_BAUDRATEPRESCALER_DIV256  (SPI_CTRL1_BRSEL)                        

#define DDL_SPI_LSB_FIRST  (SPI_CTRL1_LSBSEL)  
#define DDL_SPI_MSB_FIRST  0x00000000U         

#define DDL_SPI_FULL_DUPLEX     0x00000000U                         
#define DDL_SPI_SIMPLEX_RX      (SPI_CTRL1_RXOMEN)                  
#define DDL_SPI_HALF_DUPLEX_RX  (SPI_CTRL1_BMEN)                    
#define DDL_SPI_HALF_DUPLEX_TX  (SPI_CTRL1_BMEN | SPI_CTRL1_BMOEN)  

#define DDL_SPI_NSS_SOFT         (SPI_CTRL1_SSEN)                      
#define DDL_SPI_NSS_HARD_INPUT   0x00000000U                           
#define DDL_SPI_NSS_HARD_OUTPUT  (((uint32_t)SPI_CTRL2_SSOEN << 16U))  

#define DDL_SPI_DATAWIDTH_8BIT   0x00000000U         
#define DDL_SPI_DATAWIDTH_16BIT  (SPI_CTRL1_DFLSEL)  
#if defined(USE_FULL_DDL_DRIVER)

#define DDL_SPI_CRCCALCULATION_DISABLE  0x00000000U        
#define DDL_SPI_CRCCALCULATION_ENABLE   (SPI_CTRL1_CRCEN)  
#endif /* USE_FULL_DDL_DRIVER */

 
/* Exported macro ------------------------------------------------------------*/


#define DDL_SPI_WriteReg(__INSTANCE__,  __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

#define DDL_SPI_ReadReg(__INSTANCE__,  __REG__) READ_REG(__INSTANCE__->__REG__)

 
/* Exported functions --------------------------------------------------------*/


__STATIC_INLINE void DDL_SPI_Enable(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL1, SPI_CTRL1_SPIEN);
}

__STATIC_INLINE void DDL_SPI_Disable(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL1, SPI_CTRL1_SPIEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL1, SPI_CTRL1_SPIEN) == (SPI_CTRL1_SPIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_MSMCFG | SPI_CTRL1_ISSEL, Mode);
}

__STATIC_INLINE uint32_t DDL_SPI_GetMode(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_MSMCFG | SPI_CTRL1_ISSEL));
}

__STATIC_INLINE void DDL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
  MODIFY_REG(SPIx->CTRL2, SPI_CTRL2_FRFCFG, Standard);
}

__STATIC_INLINE uint32_t DDL_SPI_GetStandard(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL2, SPI_CTRL2_FRFCFG));
}

__STATIC_INLINE void DDL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_CPHA, ClockPhase);
}

__STATIC_INLINE uint32_t DDL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_CPHA));
}

__STATIC_INLINE void DDL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_CPOL, ClockPolarity);
}

__STATIC_INLINE uint32_t DDL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_CPOL));
}

__STATIC_INLINE void DDL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_BRSEL, BaudRate);
}

__STATIC_INLINE uint32_t DDL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_BRSEL));
}

__STATIC_INLINE void DDL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_LSBSEL, BitOrder);
}

__STATIC_INLINE uint32_t DDL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_LSBSEL));
}

__STATIC_INLINE void DDL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_RXOMEN | SPI_CTRL1_BMEN | SPI_CTRL1_BMOEN, TransferDirection);
}

__STATIC_INLINE uint32_t DDL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_RXOMEN | SPI_CTRL1_BMEN | SPI_CTRL1_BMOEN));
}

__STATIC_INLINE void DDL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_DFLSEL, DataWidth);
}

__STATIC_INLINE uint32_t DDL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CTRL1, SPI_CTRL1_DFLSEL));
}



__STATIC_INLINE void DDL_SPI_BISS_EnableBiss(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->BCR, SPI_BCR_BISS_EN);
}

__STATIC_INLINE void DDL_SPI_BISS_DisableBiss(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->BCR, SPI_BCR_BISS_EN);
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_IsEnabledBiss(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->BCR, SPI_BCR_BISS_EN) == SPI_BCR_BISS_EN) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_BISS_EnableSsi(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->BCR, SPI_BCR_SSI_EN);
}

__STATIC_INLINE void DDL_SPI_BISS_DisableSsi(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->BCR, SPI_BCR_SSI_EN);
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_IsEnabledSsi(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->BCR, SPI_BCR_SSI_EN) == SPI_BCR_SSI_EN) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_BISS_EnableStop(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->BCR, SPI_BCR_STOP_EN);
}

__STATIC_INLINE void DDL_SPI_BISS_DisableStop(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->BCR, SPI_BCR_STOP_EN);
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_IsEnabledStop(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->BCR, SPI_BCR_STOP_EN) == SPI_BCR_STOP_EN) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_BISS_SetTimeout(SPI_TypeDef *SPIx, uint32_t Timeout)
{
  MODIFY_REG(SPIx->BCFG, SPI_BCFG_TOPER, (Timeout << SPI_BCFG_TOPER_Pos) );
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_GetTimeout(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->BCFG, SPI_BCFG_TOPER) >> SPI_BCFG_TOPER_Pos);
}

__STATIC_INLINE void DDL_SPI_BISS_SetFrequency(SPI_TypeDef *SPIx, uint32_t Frequency)
{
  MODIFY_REG(SPIx->BCFG, SPI_BCFG_SPISYSCLK, Frequency);
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_GetFrequency(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->BCFG, SPI_BCFG_SPISYSCLK));
}

__STATIC_INLINE uint32_t DDL_SPI_BISS_ReceiveCDMData(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_BIT(SPIx->CDMDATA, SPI_CDMDATA_DATA));
}



__STATIC_INLINE void DDL_SPI_EnableCRC(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL1, SPI_CTRL1_CRCEN);
}

__STATIC_INLINE void DDL_SPI_DisableCRC(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL1, SPI_CTRL1_CRCEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL1, SPI_CTRL1_CRCEN) == (SPI_CTRL1_CRCEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL1, SPI_CTRL1_CRCNXT);
}

__STATIC_INLINE void DDL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
{
  WRITE_REG(SPIx->CRCPOLY, (uint16_t)CRCPoly);
}

__STATIC_INLINE uint32_t DDL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_REG(SPIx->CRCPOLY));
}

__STATIC_INLINE uint32_t DDL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_REG(SPIx->RXCRC));
}

__STATIC_INLINE uint32_t DDL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
{
  return (uint32_t)(READ_REG(SPIx->TXCRC));
}



__STATIC_INLINE void DDL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
{
  MODIFY_REG(SPIx->CTRL1, SPI_CTRL1_SSEN,  NSS);
  MODIFY_REG(SPIx->CTRL2, SPI_CTRL2_SSOEN, ((uint32_t)(NSS >> 16U)));
}

__STATIC_INLINE uint32_t DDL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
  uint32_t Ssm  = (READ_BIT(SPIx->CTRL1, SPI_CTRL1_SSEN));
  uint32_t Ssoe = (READ_BIT(SPIx->CTRL2,  SPI_CTRL2_SSOEN) << 16U);
  return (Ssm | Ssoe);
}



__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_RXBNEFLG) == (SPI_STS_RXBNEFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_TXBEFLG) == (SPI_STS_TXBEFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_CRCEFLG) == (SPI_STS_CRCEFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->STS, SPI_STS_CRCEFLG);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_MEFLG) == (SPI_STS_MEFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
  __IO uint32_t tmpreg_sr;
  tmpreg_sr = SPIx->STS;
  (void) tmpreg_sr;
  CLEAR_BIT(SPIx->CTRL1, SPI_CTRL1_SPIEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_OVRFLG) == (SPI_STS_OVRFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
  __IO uint32_t tmpreg;
  tmpreg = SPIx->DATA;
  (void) tmpreg;
  tmpreg = SPIx->STS;
  (void) tmpreg;
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_BSYFLG) == (SPI_STS_BSYFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_FREFLG) == (SPI_STS_FREFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
  __IO uint32_t tmpreg;
  tmpreg = SPIx->STS;
  (void) tmpreg;
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_CDM_NE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_CDM_NE) == (SPI_STS_CDM_NE)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_SPI_IsActiveFlag_BSBUSY(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->STS, SPI_STS_BSBUSY) == (SPI_STS_BSBUSY)) ? 1UL : 0UL);
}



__STATIC_INLINE void DDL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL2, SPI_CTRL2_ERRIEN);
}

__STATIC_INLINE void DDL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL2, SPI_CTRL2_ERRIEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL2, SPI_CTRL2_ERRIEN) == (SPI_CTRL2_ERRIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL2, SPI_CTRL2_RXBNEIEN);
}

__STATIC_INLINE void DDL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL2, SPI_CTRL2_RXBNEIEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL2, SPI_CTRL2_RXBNEIEN) == (SPI_CTRL2_RXBNEIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL2, SPI_CTRL2_TXBEIEN);
}

__STATIC_INLINE void DDL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL2, SPI_CTRL2_TXBEIEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL2, SPI_CTRL2_TXBEIEN) == (SPI_CTRL2_TXBEIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_EnableIT_CDM(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->BCR, SPI_BCR_CDM_IE);
}

__STATIC_INLINE void DDL_SPI_DisableIT_CDM(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->BCR, SPI_BCR_CDM_IE);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledIT_CDM(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->BCR, SPI_BCR_CDM_IE) == SPI_BCR_CDM_IE) ? 1UL : 0UL);
}



__STATIC_INLINE void DDL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL2, SPI_CTRL2_RXDEN);
}

__STATIC_INLINE void DDL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL2, SPI_CTRL2_RXDEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL2, SPI_CTRL2_RXDEN) == (SPI_CTRL2_RXDEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->CTRL2, SPI_CTRL2_TXDEN);
}

__STATIC_INLINE void DDL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->CTRL2, SPI_CTRL2_TXDEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->CTRL2, SPI_CTRL2_TXDEN) == (SPI_CTRL2_TXDEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_SPI_EnableDMAReq_CDM(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->BCR, SPI_BCR_CDM_DMAEN);
}

__STATIC_INLINE void DDL_SPI_DisableDMAReq_CDM(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->BCR, SPI_BCR_CDM_DMAEN);
}

__STATIC_INLINE uint32_t DDL_SPI_IsEnabledDMAReq_CDM(SPI_TypeDef *SPIx)
{
  return ((READ_BIT(SPIx->BCR, SPI_BCR_CDM_DMAEN) == SPI_BCR_CDM_DMAEN) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
  return (uint32_t) &(SPIx->DATA);
}



__STATIC_INLINE uint8_t DDL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
  return (*((__IO uint8_t *)&SPIx->DATA));
}

__STATIC_INLINE uint16_t DDL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
  return (uint16_t)(READ_REG(SPIx->DATA));
}

__STATIC_INLINE void DDL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
#if defined (__GNUC__)
  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DATA);
  *spidr = TxData;
#else
  *((__IO uint8_t *)&SPIx->DATA) = TxData;
#endif /* __GNUC__ */
}

__STATIC_INLINE void DDL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
#if defined (__GNUC__)
  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DATA);
  *spidr = TxData;
#else
  SPIx->DATA = TxData;
#endif /* __GNUC__ */
}

#if defined(USE_FULL_DDL_DRIVER)
 
ErrorStatus DDL_SPI_DeInit(SPI_TypeDef *SPIx);
ErrorStatus DDL_SPI_Init(SPI_TypeDef *SPIx, DDL_SPI_InitTypeDef *SPI_InitStruct);
void        DDL_SPI_StructInit(DDL_SPI_InitTypeDef *SPI_InitStruct);

#endif /* USE_FULL_DDL_DRIVER */

 
#endif /* SPI1 */
 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4xx_DDL_SPI_H */