g32r4xx_ddl_tmr.c

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#if defined(USE_FULL_DDL_DRIVER)
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx_ddl_tmr.h"
#include "g32r4xx_ddl_rcm.h"
 
#ifdef  USE_FULL_ASSERT
#include "g32_assert.h"
#else
#define ASSERT_PARAM(_PARAM_) ((void)0U)
#endif /* USE_FULL_ASSERT */

 
#if defined (TMR1) || defined (TMR2) || defined (TMR3) || defined (TMR4)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#define IS_DDL_TMR_COUNTERMODE(__VALUE__) (((__VALUE__) == DDL_TMR_COUNTERMODE_UP) \
                                          || ((__VALUE__) == DDL_TMR_COUNTERMODE_DOWN) \
                                          || ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_UP) \
                                          || ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_DOWN) \
                                          || ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_UP_DOWN))
 
#define IS_DDL_TMR_CLOCKDIVISION(__VALUE__) (((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV1) \
                                            || ((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV2) \
                                            || ((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV4))
 
#define IS_DDL_TMR_OCMODE(__VALUE__) (((__VALUE__) == DDL_TMR_OCMODE_FROZEN) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_ACTIVE) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_INACTIVE) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_TOGGLE) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_FORCED_INACTIVE) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_FORCED_ACTIVE) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_PWM1) \
                                     || ((__VALUE__) == DDL_TMR_OCMODE_PWM2))
 
#define IS_DDL_TMR_OCSTATE(__VALUE__) (((__VALUE__) == DDL_TMR_OCSTATE_DISABLE) \
                                      || ((__VALUE__) == DDL_TMR_OCSTATE_ENABLE))
 
#define IS_DDL_TMR_OCPOLARITY(__VALUE__) (((__VALUE__) == DDL_TMR_OCPOLARITY_HIGH) \
                                         || ((__VALUE__) == DDL_TMR_OCPOLARITY_LOW))
 
#define IS_DDL_TMR_OCIDLESTATE(__VALUE__) (((__VALUE__) == DDL_TMR_OCIDLESTATE_LOW) \
                                          || ((__VALUE__) == DDL_TMR_OCIDLESTATE_HIGH))
 
#define IS_DDL_TMR_ACTIVEINPUT(__VALUE__) (((__VALUE__) == DDL_TMR_ACTIVEINPUT_DIRECTTI) \
                                          || ((__VALUE__) == DDL_TMR_ACTIVEINPUT_INDIRECTTI) \
                                          || ((__VALUE__) == DDL_TMR_ACTIVEINPUT_TRC))
 
#define IS_DDL_TMR_ICPSC(__VALUE__) (((__VALUE__) == DDL_TMR_ICPSC_DIV1) \
                                    || ((__VALUE__) == DDL_TMR_ICPSC_DIV2) \
                                    || ((__VALUE__) == DDL_TMR_ICPSC_DIV4) \
                                    || ((__VALUE__) == DDL_TMR_ICPSC_DIV8))
 
#define IS_DDL_TMR_IC_FILTER(__VALUE__) (((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N2) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N4) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N8) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV2_N6) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV2_N8) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV4_N6) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV4_N8) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV8_N6) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV8_N8) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N5) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N6) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N8) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N5) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N6) \
                                        || ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N8))
 
#define IS_DDL_TMR_IC_POLARITY(__VALUE__) (((__VALUE__) == DDL_TMR_IC_POLARITY_RISING) \
                                          || ((__VALUE__) == DDL_TMR_IC_POLARITY_FALLING) \
                                          || ((__VALUE__) == DDL_TMR_IC_POLARITY_BOTHEDGE))
 
#define IS_DDL_TMR_ENCODERMODE(__VALUE__) (((__VALUE__) == DDL_TMR_ENCODERMODE_X2_TI1) \
                                          || ((__VALUE__) == DDL_TMR_ENCODERMODE_X2_TI2) \
                                          || ((__VALUE__) == DDL_TMR_ENCODERMODE_X4_TI12))
 
#define IS_DDL_TMR_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == DDL_TMR_IC_POLARITY_RISING) \
                                                  || ((__VALUE__) == DDL_TMR_IC_POLARITY_FALLING))
 
#define IS_DDL_TMR_OSSR_STATE(__VALUE__) (((__VALUE__) == DDL_TMR_OSSR_DISABLE) \
                                         || ((__VALUE__) == DDL_TMR_OSSR_ENABLE))
 
#define IS_DDL_TMR_OSSI_STATE(__VALUE__) (((__VALUE__) == DDL_TMR_OSSI_DISABLE) \
                                         || ((__VALUE__) == DDL_TMR_OSSI_ENABLE))
 
#define IS_DDL_TMR_LOCK_LEVEL(__VALUE__) (((__VALUE__) == DDL_TMR_LOCKLEVEL_OFF) \
                                         || ((__VALUE__) == DDL_TMR_LOCKLEVEL_1)   \
                                         || ((__VALUE__) == DDL_TMR_LOCKLEVEL_2)   \
                                         || ((__VALUE__) == DDL_TMR_LOCKLEVEL_3))
 
#define IS_DDL_TMR_BREAK_STATE(__VALUE__) (((__VALUE__) == DDL_TMR_BREAK_DISABLE) \
                                          || ((__VALUE__) == DDL_TMR_BREAK_ENABLE))
 
#define IS_DDL_TMR_BREAK_POLARITY(__VALUE__) (((__VALUE__) == DDL_TMR_BREAK_POLARITY_LOW) \
                                             || ((__VALUE__) == DDL_TMR_BREAK_POLARITY_HIGH))
 
#define IS_DDL_TMR_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == DDL_TMR_AUTOMATICOUTPUT_DISABLE) \
                                                     || ((__VALUE__) == DDL_TMR_AUTOMATICOUTPUT_ENABLE))

 
 
/* Private function prototypes -----------------------------------------------*/
static ErrorStatus OC1Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct);
static ErrorStatus OC2Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct);
static ErrorStatus OC3Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct);
static ErrorStatus OC4Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct);
static ErrorStatus IC1Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct);
static ErrorStatus IC2Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct);
static ErrorStatus IC3Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct);
static ErrorStatus IC4Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct);
 
/* Exported functions --------------------------------------------------------*/


ErrorStatus DDL_TMR_DeInit(TMR_TypeDef *TMRx)
{
  ErrorStatus result = SUCCESS;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_INSTANCE(TMRx));
 
  DDL_RCM_Unlock();
 
  if (TMRx == TMR1)
  {
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_TMR1);
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_TMR1);
  }
 
#if defined(TMR2)
  if (TMRx == TMR2)
  {
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_TMR2);
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_TMR2);
  }
#endif /* TMR3 */
#if defined(TMR3)
  else if (TMRx == TMR3)
  {
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_TMR3);
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_TMR3);
  }
#endif /* TMR3 */
#if defined(TMR4)
  else if (TMRx == TMR4)
  {
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_TMR4);
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_TMR4);
  }
#endif /* TMR4 */
  else
  {
    result = ERROR;
  }
 
  return result;
}

void DDL_TMR_StructInit(DDL_TMR_InitTypeDef *TMR_InitStruct)
{
  /* Set the default configuration */
  TMR_InitStruct->Prescaler         = (uint16_t)0x0000;
  TMR_InitStruct->CounterMode       = DDL_TMR_COUNTERMODE_UP;
  TMR_InitStruct->Autoreload        = 0xFFFFFFFFU;
  TMR_InitStruct->ClockDivision     = DDL_TMR_CLOCKDIVISION_DIV1;
  TMR_InitStruct->RepetitionCounter = 0x00000000U;
}

ErrorStatus DDL_TMR_Init(TMR_TypeDef *TMRx, DDL_TMR_InitTypeDef *TMR_InitStruct)
{
  uint32_t tmpcr1;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_COUNTERMODE(TMR_InitStruct->CounterMode));
  ASSERT_PARAM(IS_DDL_TMR_CLOCKDIVISION(TMR_InitStruct->ClockDivision));
 
  tmpcr1 = DDL_TMR_ReadReg(TMRx, CTRL1);
 
  if (IS_TMR_COUNTER_MODE_SELECT_INSTANCE(TMRx))
  {
    /* Select the Counter Mode */
    MODIFY_REG(tmpcr1, (TMR_CTRL1_CNTDIR | TMR_CTRL1_CAMSEL), TMR_InitStruct->CounterMode);
  }
 
  if (IS_TMR_CLOCK_DIVISION_INSTANCE(TMRx))
  {
    /* Set the clock division */
    MODIFY_REG(tmpcr1, TMR_CTRL1_CLKDIV, TMR_InitStruct->ClockDivision);
  }
 
  /* Write to TMRx CTRL1 */
  DDL_TMR_WriteReg(TMRx, CTRL1, tmpcr1);
 
  /* Set the Autoreload value */
  DDL_TMR_SetAutoReload(TMRx, TMR_InitStruct->Autoreload);
 
  /* Set the Prescaler value */
  DDL_TMR_SetPrescaler(TMRx, TMR_InitStruct->Prescaler);
 
  if (IS_TMR_REPETITION_COUNTER_INSTANCE(TMRx))
  {
    /* Set the Repetition Counter value */
    DDL_TMR_SetRepetitionCounter(TMRx, TMR_InitStruct->RepetitionCounter);
  }
 
  /* Generate an update event to reload the Prescaler
     and the repetition counter value  immediately */
  DDL_TMR_GenerateEvent_UPDATE(TMRx);
 
  return SUCCESS;
}

void DDL_TMR_OC_StructInit(DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct)
{
  /* Set the default configuration */
  TMR_OC_InitStruct->OCMode       = DDL_TMR_OCMODE_FROZEN;
  TMR_OC_InitStruct->OCState      = DDL_TMR_OCSTATE_DISABLE;
  TMR_OC_InitStruct->OCNState     = DDL_TMR_OCSTATE_DISABLE;
  TMR_OC_InitStruct->CompareValue = 0x00000000U;
  TMR_OC_InitStruct->OCPolarity   = DDL_TMR_OCPOLARITY_HIGH;
  TMR_OC_InitStruct->OCNPolarity  = DDL_TMR_OCPOLARITY_HIGH;
  TMR_OC_InitStruct->OCIdleState  = DDL_TMR_OCIDLESTATE_LOW;
  TMR_OC_InitStruct->OCNIdleState = DDL_TMR_OCIDLESTATE_LOW;
}

ErrorStatus DDL_TMR_OC_Init(TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct)
{
  ErrorStatus result = ERROR;
 
  switch (Channel)
  {
    case DDL_TMR_CHANNEL_CH1:
      result = OC1Config(TMRx, TMR_OC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH2:
      result = OC2Config(TMRx, TMR_OC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH3:
      result = OC3Config(TMRx, TMR_OC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH4:
      result = OC4Config(TMRx, TMR_OC_InitStruct);
      break;
    default:
      break;
  }
 
  return result;
}

void DDL_TMR_IC_StructInit(DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
{
  /* Set the default configuration */
  TMR_ICInitStruct->ICPolarity    = DDL_TMR_IC_POLARITY_RISING;
  TMR_ICInitStruct->ICActiveInput = DDL_TMR_ACTIVEINPUT_DIRECTTI;
  TMR_ICInitStruct->ICPrescaler   = DDL_TMR_ICPSC_DIV1;
  TMR_ICInitStruct->ICFilter      = DDL_TMR_IC_FILTER_FDIV1;
}

ErrorStatus DDL_TMR_IC_Init(TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_IC_InitTypeDef *TMR_IC_InitStruct)
{
  ErrorStatus result = ERROR;
 
  switch (Channel)
  {
    case DDL_TMR_CHANNEL_CH1:
      result = IC1Config(TMRx, TMR_IC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH2:
      result = IC2Config(TMRx, TMR_IC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH3:
      result = IC3Config(TMRx, TMR_IC_InitStruct);
      break;
    case DDL_TMR_CHANNEL_CH4:
      result = IC4Config(TMRx, TMR_IC_InitStruct);
      break;
    default:
      break;
  }
 
  return result;
}

void DDL_TMR_ENCODER_StructInit(DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct)
{
  /* Set the default configuration */
  TMR_EncoderInitStruct->EncoderMode    = DDL_TMR_ENCODERMODE_X2_TI1;
  TMR_EncoderInitStruct->IC1Polarity    = DDL_TMR_IC_POLARITY_RISING;
  TMR_EncoderInitStruct->IC1ActiveInput = DDL_TMR_ACTIVEINPUT_DIRECTTI;
  TMR_EncoderInitStruct->IC1Prescaler   = DDL_TMR_ICPSC_DIV1;
  TMR_EncoderInitStruct->IC1Filter      = DDL_TMR_IC_FILTER_FDIV1;
  TMR_EncoderInitStruct->IC2Polarity    = DDL_TMR_IC_POLARITY_RISING;
  TMR_EncoderInitStruct->IC2ActiveInput = DDL_TMR_ACTIVEINPUT_DIRECTTI;
  TMR_EncoderInitStruct->IC2Prescaler   = DDL_TMR_ICPSC_DIV1;
  TMR_EncoderInitStruct->IC2Filter      = DDL_TMR_IC_FILTER_FDIV1;
}

ErrorStatus DDL_TMR_ENCODER_Init(TMR_TypeDef *TMRx, DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct)
{
  uint32_t tmpccmr1;
  uint32_t tmpccer;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_ENCODER_INTERFACE_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_ENCODERMODE(TMR_EncoderInitStruct->EncoderMode));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY_ENCODER(TMR_EncoderInitStruct->IC1Polarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_EncoderInitStruct->IC1ActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_EncoderInitStruct->IC1Prescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_EncoderInitStruct->IC1Filter));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY_ENCODER(TMR_EncoderInitStruct->IC2Polarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_EncoderInitStruct->IC2ActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_EncoderInitStruct->IC2Prescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_EncoderInitStruct->IC2Filter));
 
  /* Disable the CC1 and CC2: Reset the CC1EN and CC2EN Bits */
  TMRx->CCEN &= (uint32_t)~(TMR_CCEN_CC1EN | TMR_CCEN_CC2EN);
 
  /* Get the TMRx CCM1 register value */
  tmpccmr1 = DDL_TMR_ReadReg(TMRx, CCM1);
 
  /* Get the TMRx CCEN register value */
  tmpccer = DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Configure TI1 */
  tmpccmr1 &= (uint32_t)~(TMR_CCM1_CC1SEL | TMR_CCM1_IC1F  | TMR_CCM1_IC1PSC);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC1ActiveInput);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC1Filter);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC1Prescaler);
 
  /* Configure TI2 */
  tmpccmr1 &= (uint32_t)~(TMR_CCM1_CC2SEL | TMR_CCM1_IC2F  | TMR_CCM1_IC2PSC);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC2ActiveInput << 8U);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC2Filter << 8U);
  tmpccmr1 |= (uint32_t)(TMR_EncoderInitStruct->IC2Prescaler << 8U);
 
  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  tmpccer &= (uint32_t)~(TMR_CCEN_CC1POL | TMR_CCEN_CC1NPOL | TMR_CCEN_CC2POL | TMR_CCEN_CC2NPOL);
  tmpccer |= (uint32_t)(TMR_EncoderInitStruct->IC1Polarity);
  tmpccer |= (uint32_t)(TMR_EncoderInitStruct->IC2Polarity << 4U);
  tmpccer |= (uint32_t)(TMR_CCEN_CC1EN | TMR_CCEN_CC2EN);
 
  /* Set encoder mode */
  DDL_TMR_SetEncoderMode(TMRx, TMR_EncoderInitStruct->EncoderMode);
 
  /* Write to TMRx CCM1 */
  DDL_TMR_WriteReg(TMRx, CCM1, tmpccmr1);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN, tmpccer);
 
  return SUCCESS;
}

void DDL_TMR_HALLSENSOR_StructInit(DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct)
{
  /* Set the default configuration */
  TMR_HallSensorInitStruct->IC1Polarity       = DDL_TMR_IC_POLARITY_RISING;
  TMR_HallSensorInitStruct->IC1Prescaler      = DDL_TMR_ICPSC_DIV1;
  TMR_HallSensorInitStruct->IC1Filter         = DDL_TMR_IC_FILTER_FDIV1;
  TMR_HallSensorInitStruct->CommutationDelay  = 0U;
}

ErrorStatus DDL_TMR_HALLSENSOR_Init(TMR_TypeDef *TMRx, DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct)
{
  uint32_t tmpcr2;
  uint32_t tmpccmr1;
  uint32_t tmpccer;
  uint32_t tmpsmcr;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY_ENCODER(TMR_HallSensorInitStruct->IC1Polarity));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_HallSensorInitStruct->IC1Prescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_HallSensorInitStruct->IC1Filter));
 
  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  TMRx->CCEN &= (uint32_t)~(TMR_CCEN_CC1EN | TMR_CCEN_CC2EN);
 
  /* Get the TMRx CTRL2 register value */
  tmpcr2 = DDL_TMR_ReadReg(TMRx, CTRL2);
 
  /* Get the TMRx CCM1 register value */
  tmpccmr1 = DDL_TMR_ReadReg(TMRx, CCM1);
 
  /* Get the TMRx CCEN register value */
  tmpccer = DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Get the TMRx SMCTRL register value */
  tmpsmcr = DDL_TMR_ReadReg(TMRx, SMCTRL);
 
  /* Connect TMRx_CH1, CH2 and CH3 pins to the TI1 input */
  tmpcr2 |= TMR_CTRL2_TI1SEL;
 
  /* OC2REF signal is used as trigger output (TRGO) */
  tmpcr2 |= DDL_TMR_TRGO_OC2REF;
 
  /* Configure the slave mode controller */
  tmpsmcr &= (uint32_t)~(TMR_SMCTRL_TRGSEL | TMR_SMCTRL_SMFSEL);
  tmpsmcr |= DDL_TMR_TS_TI1F_ED;
  tmpsmcr |= DDL_TMR_SLAVEMODE_RESET;
 
  /* Configure input channel 1 */
  tmpccmr1 &= (uint32_t)~(TMR_CCM1_CC1SEL | TMR_CCM1_IC1F  | TMR_CCM1_IC1PSC);
  tmpccmr1 |= (uint32_t)(DDL_TMR_ACTIVEINPUT_TRC >> 16U);
  tmpccmr1 |= (uint32_t)(TMR_HallSensorInitStruct->IC1Filter >> 16U);
  tmpccmr1 |= (uint32_t)(TMR_HallSensorInitStruct->IC1Prescaler >> 16U);
 
  /* Configure input channel 2 */
  tmpccmr1 &= (uint32_t)~(TMR_CCM1_OC2MOD | TMR_CCM1_OC2FEN  | TMR_CCM1_OC2PEN  | TMR_CCM1_OC2CEN);
  tmpccmr1 |= (uint32_t)(DDL_TMR_OCMODE_PWM2 << 8U);
 
  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
  tmpccer &= (uint32_t)~(TMR_CCEN_CC1POL | TMR_CCEN_CC1NPOL | TMR_CCEN_CC2POL | TMR_CCEN_CC2NPOL);
  tmpccer |= (uint32_t)(TMR_HallSensorInitStruct->IC1Polarity);
  tmpccer |= (uint32_t)(TMR_CCEN_CC1EN | TMR_CCEN_CC2EN);
 
  /* Write to TMRx CTRL2 */
  DDL_TMR_WriteReg(TMRx, CTRL2, tmpcr2);
 
  /* Write to TMRx SMCTRL */
  DDL_TMR_WriteReg(TMRx, SMCTRL, tmpsmcr);
 
  /* Write to TMRx CCM1 */
  DDL_TMR_WriteReg(TMRx, CCM1, tmpccmr1);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN, tmpccer);
 
  /* Write to TMRx CC2 */
  DDL_TMR_OC_SetCompareCH2(TMRx, TMR_HallSensorInitStruct->CommutationDelay);
 
  return SUCCESS;
}

void DDL_TMR_BDT_StructInit(DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct)
{
  /* Set the default configuration */
  TMR_BDTInitStruct->OSSRState       = DDL_TMR_OSSR_DISABLE;
  TMR_BDTInitStruct->OSSIState       = DDL_TMR_OSSI_DISABLE;
  TMR_BDTInitStruct->LockLevel       = DDL_TMR_LOCKLEVEL_OFF;
  TMR_BDTInitStruct->DeadTime        = (uint8_t)0x00;
  TMR_BDTInitStruct->BreakState      = DDL_TMR_BREAK_DISABLE;
  TMR_BDTInitStruct->BreakPolarity   = DDL_TMR_BREAK_POLARITY_LOW;
  TMR_BDTInitStruct->AutomaticOutput = DDL_TMR_AUTOMATICOUTPUT_DISABLE;
}

ErrorStatus DDL_TMR_BDT_Init(TMR_TypeDef *TMRx, DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct)
{
  uint32_t tmpbdtr = 0;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_BREAK_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_OSSR_STATE(TMR_BDTInitStruct->OSSRState));
  ASSERT_PARAM(IS_DDL_TMR_OSSI_STATE(TMR_BDTInitStruct->OSSIState));
  ASSERT_PARAM(IS_DDL_TMR_LOCK_LEVEL(TMR_BDTInitStruct->LockLevel));
  ASSERT_PARAM(IS_DDL_TMR_BREAK_STATE(TMR_BDTInitStruct->BreakState));
  ASSERT_PARAM(IS_DDL_TMR_BREAK_POLARITY(TMR_BDTInitStruct->BreakPolarity));
  ASSERT_PARAM(IS_DDL_TMR_AUTOMATIC_OUTPUT_STATE(TMR_BDTInitStruct->AutomaticOutput));
 
  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
  the OSSI State, the dead time value and the Automatic Output Enable Bit */
 
  /* Set the BDT bits */
  MODIFY_REG(tmpbdtr, TMR_BDT_DTS, TMR_BDTInitStruct->DeadTime);
  MODIFY_REG(tmpbdtr, TMR_BDT_LOCKCFG, TMR_BDTInitStruct->LockLevel);
  MODIFY_REG(tmpbdtr, TMR_BDT_IMOS, TMR_BDTInitStruct->OSSIState);
  MODIFY_REG(tmpbdtr, TMR_BDT_RMOS, TMR_BDTInitStruct->OSSRState);
  MODIFY_REG(tmpbdtr, TMR_BDT_BRKEN, TMR_BDTInitStruct->BreakState);
  MODIFY_REG(tmpbdtr, TMR_BDT_BRKPOL, TMR_BDTInitStruct->BreakPolarity);
  MODIFY_REG(tmpbdtr, TMR_BDT_AOEN, TMR_BDTInitStruct->AutomaticOutput);
  MODIFY_REG(tmpbdtr, TMR_BDT_MOEN, TMR_BDTInitStruct->AutomaticOutput);
 
  /* Set TMRx_BDT */
  DDL_TMR_WriteReg(TMRx, BDT, tmpbdtr);
 
  return SUCCESS;
}



static ErrorStatus OC1Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct)
{
  uint32_t tmpccmr1;
  uint32_t tmpccer;
  uint32_t tmpcr2;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC1_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_OCMODE(TMR_OCInitStruct->OCMode));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCPolarity));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCNState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCNPolarity));
 
  /* Disable the Channel 1: Reset the CC1E Bit */
  CLEAR_BIT(TMRx->CCEN, TMR_CCEN_CC1EN);
 
  /* Get the TMRx CCEN register value */
  tmpccer = DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Get the TMRx CTRL2 register value */
  tmpcr2 = DDL_TMR_ReadReg(TMRx, CTRL2);
 
  /* Get the TMRx CCM1 register value */
  tmpccmr1 = DDL_TMR_ReadReg(TMRx, CCM1);
 
  /* Reset Capture/Compare selection Bits */
  CLEAR_BIT(tmpccmr1, TMR_CCM1_CC1SEL);
 
  /* Set the Output Compare Mode */
  MODIFY_REG(tmpccmr1, TMR_CCM1_OC1MOD, TMR_OCInitStruct->OCMode);
 
  /* Set the Output Compare Polarity */
  MODIFY_REG(tmpccer, TMR_CCEN_CC1POL, TMR_OCInitStruct->OCPolarity);
 
  /* Set the Output State */
  MODIFY_REG(tmpccer, TMR_CCEN_CC1EN, TMR_OCInitStruct->OCState);
 
  if (IS_TMR_BREAK_INSTANCE(TMRx))
  {
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCNIdleState));
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCIdleState));
 
    /* Set the complementary output Polarity */
    MODIFY_REG(tmpccer, TMR_CCEN_CC1NPOL, TMR_OCInitStruct->OCNPolarity << 2U);
 
    /* Set the complementary output State */
    MODIFY_REG(tmpccer, TMR_CCEN_CC1NEN, TMR_OCInitStruct->OCNState << 2U);
 
    /* Set the Output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC1OIS, TMR_OCInitStruct->OCIdleState);
 
    /* Set the complementary output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC1NOIS, TMR_OCInitStruct->OCNIdleState << 1U);
  }
 
  /* Write to TMRx CTRL2 */
  DDL_TMR_WriteReg(TMRx, CTRL2, tmpcr2);
 
  /* Write to TMRx CCM1 */
  DDL_TMR_WriteReg(TMRx, CCM1, tmpccmr1);
 
  /* Set the Capture Compare Register value */
  DDL_TMR_OC_SetCompareCH1(TMRx, TMR_OCInitStruct->CompareValue);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN, tmpccer);
 
  return SUCCESS;
}

static ErrorStatus OC2Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct)
{
  uint32_t tmpccmr1;
  uint32_t tmpccer;
  uint32_t tmpcr2;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC2_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_OCMODE(TMR_OCInitStruct->OCMode));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCPolarity));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCNState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCNPolarity));
 
  /* Disable the Channel 2: Reset the CC2E Bit */
  CLEAR_BIT(TMRx->CCEN, TMR_CCEN_CC2EN);
 
  /* Get the TMRx CCEN register value */
  tmpccer =  DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Get the TMRx CTRL2 register value */
  tmpcr2 = DDL_TMR_ReadReg(TMRx, CTRL2);
 
  /* Get the TMRx CCM1 register value */
  tmpccmr1 = DDL_TMR_ReadReg(TMRx, CCM1);
 
  /* Reset Capture/Compare selection Bits */
  CLEAR_BIT(tmpccmr1, TMR_CCM1_CC2SEL);
 
  /* Select the Output Compare Mode */
  MODIFY_REG(tmpccmr1, TMR_CCM1_OC2MOD, TMR_OCInitStruct->OCMode << 8U);
 
  /* Set the Output Compare Polarity */
  MODIFY_REG(tmpccer, TMR_CCEN_CC2POL, TMR_OCInitStruct->OCPolarity << 4U);
 
  /* Set the Output State */
  MODIFY_REG(tmpccer, TMR_CCEN_CC2EN, TMR_OCInitStruct->OCState << 4U);
 
  if (IS_TMR_BREAK_INSTANCE(TMRx))
  {
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCNIdleState));
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCIdleState));
 
    /* Set the complementary output Polarity */
    MODIFY_REG(tmpccer, TMR_CCEN_CC2NPOL, TMR_OCInitStruct->OCNPolarity << 6U);
 
    /* Set the complementary output State */
    MODIFY_REG(tmpccer, TMR_CCEN_CC2NEN, TMR_OCInitStruct->OCNState << 6U);
 
    /* Set the Output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC2OIS, TMR_OCInitStruct->OCIdleState << 2U);
 
    /* Set the complementary output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC2NOIS, TMR_OCInitStruct->OCNIdleState << 3U);
  }
 
  /* Write to TMRx CTRL2 */
  DDL_TMR_WriteReg(TMRx, CTRL2, tmpcr2);
 
  /* Write to TMRx CCM1 */
  DDL_TMR_WriteReg(TMRx, CCM1, tmpccmr1);
 
  /* Set the Capture Compare Register value */
  DDL_TMR_OC_SetCompareCH2(TMRx, TMR_OCInitStruct->CompareValue);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN, tmpccer);
 
  return SUCCESS;
}

static ErrorStatus OC3Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct)
{
  uint32_t tmpccmr2;
  uint32_t tmpccer;
  uint32_t tmpcr2;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC3_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_OCMODE(TMR_OCInitStruct->OCMode));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCPolarity));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCNState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCNPolarity));
 
  /* Disable the Channel 3: Reset the CC3E Bit */
  CLEAR_BIT(TMRx->CCEN, TMR_CCEN_CC3EN);
 
  /* Get the TMRx CCEN register value */
  tmpccer =  DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Get the TMRx CTRL2 register value */
  tmpcr2 = DDL_TMR_ReadReg(TMRx, CTRL2);
 
  /* Get the TMRx CCM2 register value */
  tmpccmr2 = DDL_TMR_ReadReg(TMRx, CCM2);
 
  /* Reset Capture/Compare selection Bits */
  CLEAR_BIT(tmpccmr2, TMR_CCM2_CC3SEL);
 
  /* Select the Output Compare Mode */
  MODIFY_REG(tmpccmr2, TMR_CCM2_OC3MOD, TMR_OCInitStruct->OCMode);
 
  /* Set the Output Compare Polarity */
  MODIFY_REG(tmpccer, TMR_CCEN_CC3POL, TMR_OCInitStruct->OCPolarity << 8U);
 
  /* Set the Output State */
  MODIFY_REG(tmpccer, TMR_CCEN_CC3EN, TMR_OCInitStruct->OCState << 8U);
 
  if (IS_TMR_BREAK_INSTANCE(TMRx))
  {
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCNIdleState));
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCIdleState));
 
    /* Set the complementary output Polarity */
    MODIFY_REG(tmpccer, TMR_CCEN_CC3NPOL, TMR_OCInitStruct->OCNPolarity << 10U);
 
    /* Set the complementary output State */
    MODIFY_REG(tmpccer, TMR_CCEN_CC3NEN, TMR_OCInitStruct->OCNState << 10U);
 
    /* Set the Output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC3OIS, TMR_OCInitStruct->OCIdleState << 4U);
 
    /* Set the complementary output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC3NOIS, TMR_OCInitStruct->OCNIdleState << 5U);
  }
 
  /* Write to TMRx CTRL2 */
  DDL_TMR_WriteReg(TMRx, CTRL2, tmpcr2);
 
  /* Write to TMRx CCM2 */
  DDL_TMR_WriteReg(TMRx, CCM2, tmpccmr2);
 
  /* Set the Capture Compare Register value */
  DDL_TMR_OC_SetCompareCH3(TMRx, TMR_OCInitStruct->CompareValue);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN, tmpccer);
 
  return SUCCESS;
}

static ErrorStatus OC4Config(TMR_TypeDef *TMRx, DDL_TMR_OC_InitTypeDef *TMR_OCInitStruct)
{
  uint32_t tmpccmr2;
  uint32_t tmpccer;
  uint32_t tmpcr2;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC4_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_OCMODE(TMR_OCInitStruct->OCMode));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCState));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCPolarity));
  ASSERT_PARAM(IS_DDL_TMR_OCPOLARITY(TMR_OCInitStruct->OCNPolarity));
  ASSERT_PARAM(IS_DDL_TMR_OCSTATE(TMR_OCInitStruct->OCNState));
 
  /* Disable the Channel 4: Reset the CC4E Bit */
  CLEAR_BIT(TMRx->CCEN, TMR_CCEN_CC4EN);
 
  /* Get the TMRx CCEN register value */
  tmpccer = DDL_TMR_ReadReg(TMRx, CCEN);
 
  /* Get the TMRx CTRL2 register value */
  tmpcr2 =  DDL_TMR_ReadReg(TMRx, CTRL2);
 
  /* Get the TMRx CCM2 register value */
  tmpccmr2 = DDL_TMR_ReadReg(TMRx, CCM2);
 
  /* Reset Capture/Compare selection Bits */
  CLEAR_BIT(tmpccmr2, TMR_CCM2_CC4SEL);
 
  /* Select the Output Compare Mode */
  MODIFY_REG(tmpccmr2, TMR_CCM2_OC4MOD, TMR_OCInitStruct->OCMode << 8U);
 
  /* Set the Output Compare Polarity */
  MODIFY_REG(tmpccer, TMR_CCEN_CC4POL, TMR_OCInitStruct->OCPolarity << 12U);
 
  /* Set the Output State */
  MODIFY_REG(tmpccer, TMR_CCEN_CC4EN, TMR_OCInitStruct->OCState << 12U);
 
  if (IS_TMR_BREAK_INSTANCE(TMRx))
  {
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCNIdleState));
    ASSERT_PARAM(IS_DDL_TMR_OCIDLESTATE(TMR_OCInitStruct->OCIdleState));
 
    /* Set the Output Idle state */
    MODIFY_REG(tmpcr2, TMR_CTRL2_OC4OIS, TMR_OCInitStruct->OCIdleState << 6U);
  }
 
  /* Write to TMRx CTRL2 */
  DDL_TMR_WriteReg(TMRx, CTRL2, tmpcr2);
 
  /* Write to TMRx CCM2 */
  DDL_TMR_WriteReg(TMRx, CCM2, tmpccmr2);
 
  /* Set the Capture Compare Register value */
  DDL_TMR_OC_SetCompareCH4(TMRx, TMR_OCInitStruct->CompareValue);
 
  /* Write to TMRx CCEN */
  DDL_TMR_WriteReg(TMRx, CCEN , tmpccer);
 
  return SUCCESS;
}
 

static ErrorStatus IC1Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
{
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC1_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY(TMR_ICInitStruct->ICPolarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_ICInitStruct->ICActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_ICInitStruct->ICPrescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_ICInitStruct->ICFilter));
 
  /* Disable the Channel 1: Reset the CC1E Bit */
  TMRx->CCEN &= (uint32_t)~TMR_CCEN_CC1EN;
 
  /* Select the Input and set the filter and the prescaler value */
  MODIFY_REG(TMRx->CCM1,
             (TMR_CCM1_CC1SEL | TMR_CCM1_IC1F | TMR_CCM1_IC1PSC),
             (TMR_ICInitStruct->ICActiveInput | TMR_ICInitStruct->ICFilter | TMR_ICInitStruct->ICPrescaler));
 
  /* Select the Polarity and set the CC1E Bit */
  MODIFY_REG(TMRx->CCEN,
             (TMR_CCEN_CC1POL | TMR_CCEN_CC1NPOL),
             (TMR_ICInitStruct->ICPolarity | TMR_CCEN_CC1EN));
 
  return SUCCESS;
}

static ErrorStatus IC2Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
{
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC2_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY(TMR_ICInitStruct->ICPolarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_ICInitStruct->ICActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_ICInitStruct->ICPrescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_ICInitStruct->ICFilter));
 
  /* Disable the Channel 2: Reset the CC2E Bit */
  TMRx->CCEN &= (uint32_t)~TMR_CCEN_CC2EN;
 
  /* Select the Input and set the filter and the prescaler value */
  MODIFY_REG(TMRx->CCM1,
             (TMR_CCM1_CC2SEL | TMR_CCM1_IC2F | TMR_CCM1_IC2PSC),
             (TMR_ICInitStruct->ICActiveInput | TMR_ICInitStruct->ICFilter | TMR_ICInitStruct->ICPrescaler) << 8);
 
  /* Select the Polarity and set the CC2E Bit */
  MODIFY_REG(TMRx->CCEN,
             (TMR_CCEN_CC2POL | TMR_CCEN_CC2NPOL),
             ((TMR_ICInitStruct->ICPolarity << 4U) | TMR_CCEN_CC2EN));
 
  return SUCCESS;
}

static ErrorStatus IC3Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
{
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC3_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY(TMR_ICInitStruct->ICPolarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_ICInitStruct->ICActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_ICInitStruct->ICPrescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_ICInitStruct->ICFilter));
 
  /* Disable the Channel 3: Reset the CC3E Bit */
  TMRx->CCEN &= (uint32_t)~TMR_CCEN_CC3EN;
 
  /* Select the Input and set the filter and the prescaler value */
  MODIFY_REG(TMRx->CCM2,
             (TMR_CCM2_CC3SEL | TMR_CCM2_IC3F | TMR_CCM2_IC3PSC),
             (TMR_ICInitStruct->ICActiveInput | TMR_ICInitStruct->ICFilter | TMR_ICInitStruct->ICPrescaler));
 
  /* Select the Polarity and set the CC3E Bit */
  MODIFY_REG(TMRx->CCEN,
             (TMR_CCEN_CC3POL | TMR_CCEN_CC3NPOL),
             ((TMR_ICInitStruct->ICPolarity << 8U) | TMR_CCEN_CC3EN));
 
  return SUCCESS;
}

static ErrorStatus IC4Config(TMR_TypeDef *TMRx, DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
{
  /* Check the parameters */
  ASSERT_PARAM(IS_TMR_CC4_INSTANCE(TMRx));
  ASSERT_PARAM(IS_DDL_TMR_IC_POLARITY(TMR_ICInitStruct->ICPolarity));
  ASSERT_PARAM(IS_DDL_TMR_ACTIVEINPUT(TMR_ICInitStruct->ICActiveInput));
  ASSERT_PARAM(IS_DDL_TMR_ICPSC(TMR_ICInitStruct->ICPrescaler));
  ASSERT_PARAM(IS_DDL_TMR_IC_FILTER(TMR_ICInitStruct->ICFilter));
 
  /* Disable the Channel 4: Reset the CC4E Bit */
  TMRx->CCEN &= (uint32_t)~TMR_CCEN_CC4EN;
 
  /* Select the Input and set the filter and the prescaler value */
  MODIFY_REG(TMRx->CCM2,
             (TMR_CCM2_CC4SEL | TMR_CCM2_IC4F | TMR_CCM2_IC4PSC),
             (TMR_ICInitStruct->ICActiveInput | TMR_ICInitStruct->ICFilter | TMR_ICInitStruct->ICPrescaler) << 8U);
 
  /* Select the Polarity and set the CC4E Bit */
  MODIFY_REG(TMRx->CCEN,
             (TMR_CCEN_CC4POL),
             ((TMR_ICInitStruct->ICPolarity << 12U) | TMR_CCEN_CC4EN));
 
  return SUCCESS;
}
 


 
#endif /* TMR1 || TMR2 || TMR3 || TMR4 */

 
#endif /* USE_FULL_DDL_DRIVER */