g32r4xx_ddl_tmr.h File Reference

Header file of TMR DDL module. More...

#include "g32r4xx.h"

Go to the source code of this file.

Data Structures
struct	DDL_TMR_InitTypeDef
	TMR Time Base configuration structure definition. More...
struct	DDL_TMR_OC_InitTypeDef
	TMR Output Compare configuration structure definition. More...
struct	DDL_TMR_IC_InitTypeDef
	TMR Input Capture configuration structure definition. More...
struct	DDL_TMR_ENCODER_InitTypeDef
	TMR Encoder interface configuration structure definition. More...
struct	DDL_TMR_HALLSENSOR_InitTypeDef
	TMR Hall sensor interface configuration structure definition. More...
struct	DDL_TMR_BDT_InitTypeDef
	BDTR (Break and Dead Time) structure definition. More...

Macros
#define	DT_DELAY_1   ((uint8_t)0x7F)
#define	DT_DELAY_2   ((uint8_t)0x3F)
#define	DT_DELAY_3   ((uint8_t)0x1F)
#define	DT_DELAY_4   ((uint8_t)0x1F)
#define	DT_RANGE_1   ((uint8_t)0x00)
#define	DT_RANGE_2   ((uint8_t)0x80)
#define	DT_RANGE_3   ((uint8_t)0xC0)
#define	DT_RANGE_4   ((uint8_t)0xE0)
#define	TMR_GET_CHANNEL_INDEX( __CHANNEL__)
	Convert channel id into channel index.
#define	TMR_CALC_DTS(__TMRCLK__, __CKD__)
	Calculate the deadtime sampling period(in ps).
#define	DDL_TMR_STS_UIFLG   TMR_STS_UIFLG
#define	DDL_TMR_STS_CC1IFLG   TMR_STS_CC1IFLG
#define	DDL_TMR_STS_CC2IFLG   TMR_STS_CC2IFLG
#define	DDL_TMR_STS_CC3IFLG   TMR_STS_CC3IFLG
#define	DDL_TMR_STS_CC4IFLG   TMR_STS_CC4IFLG
#define	DDL_TMR_STS_COMIFLG   TMR_STS_COMIFLG
#define	DDL_TMR_STS_TRGIFLG   TMR_STS_TRGIFLG
#define	DDL_TMR_STS_BRKIFLG   TMR_STS_BRKIFLG
#define	DDL_TMR_STS_CC1RCFLG   TMR_STS_CC1RCFLG
#define	DDL_TMR_STS_CC2RCFLG   TMR_STS_CC2RCFLG
#define	DDL_TMR_STS_CC3RCFLG   TMR_STS_CC3RCFLG
#define	DDL_TMR_STS_CC4RCFLG   TMR_STS_CC4RCFLG
#define	DDL_TMR_BREAK_DISABLE   0x00000000U
#define	DDL_TMR_BREAK_ENABLE   TMR_BDT_BRKEN
#define	DDL_TMR_AUTOMATICOUTPUT_DISABLE   0x00000000U
#define	DDL_TMR_AUTOMATICOUTPUT_ENABLE   TMR_BDT_AOEN
#define	DDL_TMR_DIEN_UIEN   TMR_DIEN_UIEN
#define	DDL_TMR_DIEN_CC1IEN   TMR_DIEN_CC1IEN
#define	DDL_TMR_DIEN_CC2IEN   TMR_DIEN_CC2IEN
#define	DDL_TMR_DIEN_CC3IEN   TMR_DIEN_CC3IEN
#define	DDL_TMR_DIEN_CC4IEN   TMR_DIEN_CC4IEN
#define	DDL_TMR_DIEN_COMIEN   TMR_DIEN_COMIEN
#define	DDL_TMR_DIEN_TRGIEN   TMR_DIEN_TRGIEN
#define	DDL_TMR_DIEN_BRKIEN   TMR_DIEN_BRKIEN
#define	DDL_TMR_UPDATESOURCE_REGULAR   0x00000000U
#define	DDL_TMR_UPDATESOURCE_COUNTER   TMR_CTRL1_URSSEL
#define	DDL_TMR_ONEPULSEMODE_SINGLE   TMR_CTRL1_SPMEN
#define	DDL_TMR_ONEPULSEMODE_REPETITIVE   0x00000000U
#define	DDL_TMR_COUNTERMODE_UP   0x00000000U
#define	DDL_TMR_COUNTERMODE_DOWN   TMR_CTRL1_CNTDIR
#define	DDL_TMR_COUNTERMODE_CENTER_DOWN   TMR_CTRL1_CAMSEL_0
#define	DDL_TMR_COUNTERMODE_CENTER_UP   TMR_CTRL1_CAMSEL_1
#define	DDL_TMR_COUNTERMODE_CENTER_UP_DOWN   TMR_CTRL1_CAMSEL
#define	DDL_TMR_CLOCKDIVISION_DIV1   0x00000000U
#define	DDL_TMR_CLOCKDIVISION_DIV2   TMR_CTRL1_CLKDIV_0
#define	DDL_TMR_CLOCKDIVISION_DIV4   TMR_CTRL1_CLKDIV_1
#define	DDL_TMR_COUNTERDIRECTION_UP   0x00000000U
#define	DDL_TMR_COUNTERDIRECTION_DOWN   TMR_CTRL1_CNTDIR
#define	DDL_TMR_CCUPDATESOURCE_COMG_ONLY   0x00000000U
#define	DDL_TMR_CCUPDATESOURCE_COMG_AND_TRGI   TMR_CTRL2_CCUSEL
#define	DDL_TMR_CCDMAREQUEST_CC   0x00000000U
#define	DDL_TMR_CCDMAREQUEST_UPDATE   TMR_CTRL2_CCDSEL
#define	DDL_TMR_LOCKLEVEL_OFF   0x00000000U
#define	DDL_TMR_LOCKLEVEL_1   TMR_BDT_LOCKCFG_0
#define	DDL_TMR_LOCKLEVEL_2   TMR_BDT_LOCKCFG_1
#define	DDL_TMR_LOCKLEVEL_3   TMR_BDT_LOCKCFG
#define	DDL_TMR_CHANNEL_CH1   TMR_CCEN_CC1EN
#define	DDL_TMR_CHANNEL_CH1N   TMR_CCEN_CC1NEN
#define	DDL_TMR_CHANNEL_CH2   TMR_CCEN_CC2EN
#define	DDL_TMR_CHANNEL_CH2N   TMR_CCEN_CC2NEN
#define	DDL_TMR_CHANNEL_CH3   TMR_CCEN_CC3EN
#define	DDL_TMR_CHANNEL_CH3N   TMR_CCEN_CC3NEN
#define	DDL_TMR_CHANNEL_CH4   TMR_CCEN_CC4EN
#define	DDL_TMR_OCSTATE_DISABLE   0x00000000U
#define	DDL_TMR_OCSTATE_ENABLE   TMR_CCEN_CC1EN
#define	DDL_TMR_OCMODE_FROZEN   (0x00000000U)
#define	DDL_TMR_OCMODE_ACTIVE   (TMR_CCM1_OC1MOD_0)
#define	DDL_TMR_OCMODE_INACTIVE   (TMR_CCM1_OC1MOD_1)
#define	DDL_TMR_OCMODE_TOGGLE   (TMR_CCM1_OC1MOD_1 | TMR_CCM1_OC1MOD_0)
#define	DDL_TMR_OCMODE_FORCED_INACTIVE   (TMR_CCM1_OC1MOD_2)
#define	DDL_TMR_OCMODE_FORCED_ACTIVE   (TMR_CCM1_OC1MOD_2 | TMR_CCM1_OC1MOD_0)
#define	DDL_TMR_OCMODE_PWM1   (TMR_CCM1_OC1MOD_2 | TMR_CCM1_OC1MOD_1)
#define	DDL_TMR_OCMODE_PWM2   (TMR_CCM1_OC1MOD)
#define	DDL_TMR_OCPOLARITY_HIGH   0x00000000U
#define	DDL_TMR_OCPOLARITY_LOW   TMR_CCEN_CC1POL
#define	DDL_TMR_OCIDLESTATE_LOW   0x00000000U
#define	DDL_TMR_OCIDLESTATE_HIGH   TMR_CTRL2_OC1OIS
#define	DDL_TMR_ACTIVEINPUT_DIRECTTI   (TMR_CCM1_CC1SEL_0)
#define	DDL_TMR_ACTIVEINPUT_INDIRECTTI   (TMR_CCM1_CC1SEL_1)
#define	DDL_TMR_ACTIVEINPUT_TRC   (TMR_CCM1_CC1SEL)
#define	DDL_TMR_ICPSC_DIV1   0x00000000U
#define	DDL_TMR_ICPSC_DIV2   (TMR_CCM1_IC1PSC_0)
#define	DDL_TMR_ICPSC_DIV4   (TMR_CCM1_IC1PSC_1)
#define	DDL_TMR_ICPSC_DIV8   (TMR_CCM1_IC1PSC)
#define	DDL_TMR_IC_FILTER_FDIV1   (0x00000000U)
#define	DDL_TMR_IC_FILTER_FDIV1_N2   (TMR_CCM1_IC1F_0)
#define	DDL_TMR_IC_FILTER_FDIV1_N4   (TMR_CCM1_IC1F_1)
#define	DDL_TMR_IC_FILTER_FDIV1_N8   ((TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV2_N6   (TMR_CCM1_IC1F_2)
#define	DDL_TMR_IC_FILTER_FDIV2_N8   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV4_N6   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1))
#define	DDL_TMR_IC_FILTER_FDIV4_N8   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV8_N6   (TMR_CCM1_IC1F_3)
#define	DDL_TMR_IC_FILTER_FDIV8_N8   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV16_N5   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_1))
#define	DDL_TMR_IC_FILTER_FDIV16_N6   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV16_N8   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2))
#define	DDL_TMR_IC_FILTER_FDIV32_N5   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_0))
#define	DDL_TMR_IC_FILTER_FDIV32_N6   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1))
#define	DDL_TMR_IC_FILTER_FDIV32_N8   (TMR_CCM1_IC1F)
#define	DDL_TMR_IC_POLARITY_RISING   0x00000000U
#define	DDL_TMR_IC_POLARITY_FALLING   TMR_CCEN_CC1POL
#define	DDL_TMR_IC_POLARITY_BOTHEDGE   (TMR_CCEN_CC1POL | TMR_CCEN_CC1NPOL)
#define	DDL_TMR_CLOCKSOURCE_INTERNAL   0x00000000U
#define	DDL_TMR_CLOCKSOURCE_EXT_MODE1   TMR_SMCTRL_SMFSEL
#define	DDL_TMR_CLOCKSOURCE_EXT_MODE2   TMR_SMCTRL_ECEN
#define	DDL_TMR_ENCODERMODE_X2_TI1   (TMR_SMCTRL_SMFSEL_0)
#define	DDL_TMR_ENCODERMODE_X2_TI2   (TMR_SMCTRL_SMFSEL_1)
#define	DDL_TMR_ENCODERMODE_X4_TI12   (TMR_SMCTRL_SMFSEL_1 | TMR_SMCTRL_SMFSEL_0)
#define	DDL_TMR_TRGO_RESET   (0x00000000U)
#define	DDL_TMR_TRGO_ENABLE   (TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_UPDATE   (TMR_CTRL2_MMSEL_1)
#define	DDL_TMR_TRGO_CC1IF   (TMR_CTRL2_MMSEL_1 | TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_OC1REF   (TMR_CTRL2_MMSEL_2)
#define	DDL_TMR_TRGO_OC2REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_OC3REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_1)
#define	DDL_TMR_TRGO_OC4REF   (TMR_CTRL2_MMSEL)
#define	DDL_TMR_SLAVEMODE_DISABLED   (0x00000000U)
#define	DDL_TMR_SLAVEMODE_RESET   (TMR_SMCTRL_SMFSEL_2)
#define	DDL_TMR_SLAVEMODE_GATED   (TMR_SMCTRL_SMFSEL_2 | TMR_SMCTRL_SMFSEL_0)
#define	DDL_TMR_SLAVEMODE_TRIGGER   (TMR_SMCTRL_SMFSEL_2 | TMR_SMCTRL_SMFSEL_1)
#define	DDL_TMR_TS_ITR0   (0x00000000U)
#define	DDL_TMR_TS_ITR1   (TMR_SMCTRL_TRGSEL_0)
#define	DDL_TMR_TS_ITR2   (TMR_SMCTRL_TRGSEL_1)
#define	DDL_TMR_TS_ITR3   (TMR_SMCTRL_TRGSEL_0 | TMR_SMCTRL_TRGSEL_1)
#define	DDL_TMR_TS_TI1F_ED   (TMR_SMCTRL_TRGSEL_2)
#define	DDL_TMR_TS_TI1FP1   (TMR_SMCTRL_TRGSEL_2 | TMR_SMCTRL_TRGSEL_0)
#define	DDL_TMR_TS_TI2FP2   (TMR_SMCTRL_TRGSEL_2 | TMR_SMCTRL_TRGSEL_1)
#define	DDL_TMR_TS_ETRF   (TMR_SMCTRL_TRGSEL)
#define	DDL_TMR_ETR_POLARITY_NONINVERTED   0x00000000U
#define	DDL_TMR_ETR_POLARITY_INVERTED   TMR_SMCTRL_ETPOL
#define	DDL_TMR_ETR_PRESCALER_DIV1   0x00000000U
#define	DDL_TMR_ETR_PRESCALER_DIV2   TMR_SMCTRL_ETPCFG_0
#define	DDL_TMR_ETR_PRESCALER_DIV4   TMR_SMCTRL_ETPCFG_1
#define	DDL_TMR_ETR_PRESCALER_DIV8   TMR_SMCTRL_ETPCFG
#define	DDL_TMR_ETR_FILTER_FDIV1   (0x00000000U)
#define	DDL_TMR_ETR_FILTER_FDIV1_N2   (TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV1_N4   (TMR_SMCTRL_ETFCFG_1)
#define	DDL_TMR_ETR_FILTER_FDIV1_N8   (TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV2_N6   (TMR_SMCTRL_ETFCFG_2)
#define	DDL_TMR_ETR_FILTER_FDIV2_N8   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV4_N6   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1)
#define	DDL_TMR_ETR_FILTER_FDIV4_N8   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV8_N6   (TMR_SMCTRL_ETFCFG_3)
#define	DDL_TMR_ETR_FILTER_FDIV8_N8   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV16_N5   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1)
#define	DDL_TMR_ETR_FILTER_FDIV16_N6   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV16_N8   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2)
#define	DDL_TMR_ETR_FILTER_FDIV32_N5   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0)
#define	DDL_TMR_ETR_FILTER_FDIV32_N6   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1)
#define	DDL_TMR_ETR_FILTER_FDIV32_N8   (TMR_SMCTRL_ETFCFG)
#define	DDL_TMR_BREAK_POLARITY_LOW   0x00000000U
#define	DDL_TMR_BREAK_POLARITY_HIGH   TMR_BDT_BRKPOL
#define	DDL_TMR_OSSI_DISABLE   0x00000000U
#define	DDL_TMR_OSSI_ENABLE   TMR_BDT_IMOS
#define	DDL_TMR_OSSR_DISABLE   0x00000000U
#define	DDL_TMR_OSSR_ENABLE   TMR_BDT_RMOS
#define	DDL_TMR_DMABURST_BASEADDR_CTRL1   (0x00000000U)
#define	DDL_TMR_DMABURST_BASEADDR_CTRL2   (TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_SMCTRL   (TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_DIEN   (TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_STS   (TMR_DCTRL_DBADDR_2)
#define	DDL_TMR_DMABURST_BASEADDR_CEG   (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CCM1   (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_CCM2   (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CCEN   (TMR_DCTRL_DBADDR_3)
#define	DDL_TMR_DMABURST_BASEADDR_CNT   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_PSC   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_AUTORLD   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_REPCNT   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2)
#define	DDL_TMR_DMABURST_BASEADDR_CC1   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CC2   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_CC3   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CC4   (TMR_DCTRL_DBADDR_4)
#define	DDL_TMR_DMABURST_BASEADDR_BDT   (TMR_DCTRL_DBADDR_4 | TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_LENGTH_1TRANSFER   (0x00000000U)
#define	DDL_TMR_DMABURST_LENGTH_2TRANSFERS   (TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_3TRANSFERS   (TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_4TRANSFERS   (TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_5TRANSFERS   (TMR_DCTRL_DBLEN_2)
#define	DDL_TMR_DMABURST_LENGTH_6TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_7TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_8TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_9TRANSFERS   (TMR_DCTRL_DBLEN_3)
#define	DDL_TMR_DMABURST_LENGTH_10TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_11TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_12TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_13TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2)
#define	DDL_TMR_DMABURST_LENGTH_14TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_15TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_16TRANSFERS   (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_17TRANSFERS   (TMR_DCTRL_DBLEN_4)
#define	DDL_TMR_DMABURST_LENGTH_18TRANSFERS   (TMR_DCTRL_DBLEN_4 | TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_WriteReg(__INSTANCE__, __REG__, __VALUE__)
	Write a value in TMR register.
#define	DDL_TMR_ReadReg(__INSTANCE__, __REG__)
	Read a value in TMR register.
#define	__DDL_TMR_CALC_DEADTMRE(__TMRCLK__, __CKD__, __DT__)
	HELPER macro calculating DTG[0:7] in the TMRx_BDTR register to achieve the requested dead time duration.
#define	__DDL_TMR_CALC_PSC(__TMRCLK__, __CNTCLK__)
	HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define	__DDL_TMR_CALC_ARR(__TMRCLK__, __PSC__, __FREQ__)
	HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define	__DDL_TMR_CALC_DELAY(__TMRCLK__, __PSC__, __DELAY__)
	HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define	__DDL_TMR_CALC_PULSE(__TMRCLK__, __PSC__, __DELAY__, __PULSE__)
	HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define	__DDL_TMR_GET_ICPSC_RATIO(__ICPSC__)
	HELPER macro retrieving the ratio of the input capture prescaler.

Functions
__STATIC_INLINE void	DDL_TMR_EnableCounter (TMR_TypeDef *TMRx)
	Enable timer counter.
__STATIC_INLINE void	DDL_TMR_DisableCounter (TMR_TypeDef *TMRx)
	Disable timer counter.
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledCounter (TMR_TypeDef *TMRx)
	Indicates whether the timer counter is enabled.
__STATIC_INLINE void	DDL_TMR_EnableUpdateEvent (TMR_TypeDef *TMRx)
	Enable update event generation.
__STATIC_INLINE void	DDL_TMR_DisableUpdateEvent (TMR_TypeDef *TMRx)
	Disable update event generation.
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledUpdateEvent (TMR_TypeDef *TMRx)
	Indicates whether update event generation is enabled.
__STATIC_INLINE void	DDL_TMR_SetUpdateSource (TMR_TypeDef *TMRx, uint32_t UpdateSource)
	Set update event source.
__STATIC_INLINE uint32_t	DDL_TMR_GetUpdateSource (TMR_TypeDef *TMRx)
	Get actual event update source.
__STATIC_INLINE void	DDL_TMR_SetOnePulseMode (TMR_TypeDef *TMRx, uint32_t OnePulseMode)
	Set one pulse mode (one shot v.s. repetitive).
__STATIC_INLINE uint32_t	DDL_TMR_GetOnePulseMode (TMR_TypeDef *TMRx)
	Get actual one pulse mode.
__STATIC_INLINE void	DDL_TMR_SetCounterMode (TMR_TypeDef *TMRx, uint32_t CounterMode)
	Set the timer counter counting mode.
__STATIC_INLINE uint32_t	DDL_TMR_GetCounterMode (TMR_TypeDef *TMRx)
	Get actual counter mode.
__STATIC_INLINE void	DDL_TMR_EnableARRPreload (TMR_TypeDef *TMRx)
	Enable auto-reload (ARR) preload.
__STATIC_INLINE void	DDL_TMR_DisableARRPreload (TMR_TypeDef *TMRx)
	Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledARRPreload (TMR_TypeDef *TMRx)
	Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void	DDL_TMR_SetClockDivision (TMR_TypeDef *TMRx, uint32_t ClockDivision)
	Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t	DDL_TMR_GetClockDivision (TMR_TypeDef *TMRx)
	Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void	DDL_TMR_SetCounter (TMR_TypeDef *TMRx, uint32_t Counter)
	Set the counter value.
__STATIC_INLINE uint32_t	DDL_TMR_GetCounter (TMR_TypeDef *TMRx)
	Get the counter value.
__STATIC_INLINE void	DDL_TMR_SetDirection (TMR_TypeDef *TMRx, uint32_t Direction)
	Set the current direction of the counter.
__STATIC_INLINE uint32_t	DDL_TMR_GetDirection (TMR_TypeDef *TMRx)
	Get the current direction of the counter.
__STATIC_INLINE void	DDL_TMR_SetPrescaler (TMR_TypeDef *TMRx, uint32_t Prescaler)
	Set the prescaler value.
__STATIC_INLINE uint32_t	DDL_TMR_GetPrescaler (TMR_TypeDef *TMRx)
	Get the prescaler value.
__STATIC_INLINE void	DDL_TMR_SetAutoReload (TMR_TypeDef *TMRx, uint32_t AutoReload)
	Set the auto-reload value.
__STATIC_INLINE uint32_t	DDL_TMR_GetAutoReload (TMR_TypeDef *TMRx)
	Get the auto-reload value.
__STATIC_INLINE void	DDL_TMR_SetRepetitionCounter (TMR_TypeDef *TMRx, uint32_t RepetitionCounter)
	Set the repetition counter value.
__STATIC_INLINE uint32_t	DDL_TMR_GetRepetitionCounter (TMR_TypeDef *TMRx)
	Get the repetition counter value.
__STATIC_INLINE void	DDL_TMR_CC_EnablePreload (TMR_TypeDef *TMRx)
	Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void	DDL_TMR_CC_DisablePreload (TMR_TypeDef *TMRx)
	Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE uint32_t	DDL_TMR_CC_IsEnabledPreload (TMR_TypeDef *TMRx)
	Indicates whether capture/compare control bits preload is enabled.
__STATIC_INLINE void	DDL_TMR_CC_SetUpdate (TMR_TypeDef *TMRx, uint32_t CCUpdateSource)
	Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE uint32_t	DDL_TMR_CC_GetUpdate (TMR_TypeDef *TMRx)
	Get the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void	DDL_TMR_CC_SetDMAReqTrigger (TMR_TypeDef *TMRx, uint32_t DMAReqTrigger)
	Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t	DDL_TMR_CC_GetDMAReqTrigger (TMR_TypeDef *TMRx)
	Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void	DDL_TMR_CC_SetLockLevel (TMR_TypeDef *TMRx, uint32_t LockLevel)
	Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void	DDL_TMR_CC_EnableChannel (TMR_TypeDef *TMRx, uint32_t Channels)
	Enable capture/compare channels.
__STATIC_INLINE void	DDL_TMR_CC_DisableChannel (TMR_TypeDef *TMRx, uint32_t Channels)
	Disable capture/compare channels.
__STATIC_INLINE uint32_t	DDL_TMR_CC_IsEnabledChannel (TMR_TypeDef *TMRx, uint32_t Channels)
	Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void	DDL_TMR_OC_ConfigOutput (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Configuration)
	Configure an output channel.
__STATIC_INLINE void	DDL_TMR_OC_SetMode (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Mode)
	Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetMode (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the output compare mode of an output channel.
__STATIC_INLINE void	DDL_TMR_OC_SetPolarity (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Polarity)
	Set the polarity of an output channel.
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetPolarity (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the polarity of an output channel.
__STATIC_INLINE void	DDL_TMR_OC_SetIdleState (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t IdleState)
	Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetIdleState (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the IDLE state of an output channel.
__STATIC_INLINE void	DDL_TMR_OC_EnableFast (TMR_TypeDef *TMRx, uint32_t Channel)
	Enable fast mode for the output channel.
__STATIC_INLINE void	DDL_TMR_OC_DisableFast (TMR_TypeDef *TMRx, uint32_t Channel)
	Disable fast mode for the output channel.
__STATIC_INLINE uint32_t	DDL_TMR_OC_IsEnabledFast (TMR_TypeDef *TMRx, uint32_t Channel)
	Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void	DDL_TMR_OC_EnablePreload (TMR_TypeDef *TMRx, uint32_t Channel)
	Enable compare register (TMRx_CCx) preload for the output channel.
__STATIC_INLINE void	DDL_TMR_OC_DisablePreload (TMR_TypeDef *TMRx, uint32_t Channel)
	Disable compare register (TMRx_CCx) preload for the output channel.
__STATIC_INLINE uint32_t	DDL_TMR_OC_IsEnabledPreload (TMR_TypeDef *TMRx, uint32_t Channel)
	Indicates whether compare register (TMRx_CCx) preload is enabled for the output channel.
__STATIC_INLINE void	DDL_TMR_OC_EnableClear (TMR_TypeDef *TMRx, uint32_t Channel)
	Enable clearing the output channel on an external event.
__STATIC_INLINE void	DDL_TMR_OC_DisableClear (TMR_TypeDef *TMRx, uint32_t Channel)
	Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t	DDL_TMR_OC_IsEnabledClear (TMR_TypeDef *TMRx, uint32_t Channel)
	Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void	DDL_TMR_OC_SetDeadTime (TMR_TypeDef *TMRx, uint32_t DeadTime)
	Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
__STATIC_INLINE void	DDL_TMR_OC_SetCompareCH1 (TMR_TypeDef *TMRx, uint32_t CompareValue)
	Set compare value for output channel 1 (TMRx_CC1).
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetCompareCH1 (TMR_TypeDef *TMRx)
	Get compare value (TMRx_CC1) set for output channel 1.
__STATIC_INLINE void	DDL_TMR_OC_SetCompareCH2 (TMR_TypeDef *TMRx, uint32_t CompareValue)
	Set compare value for output channel 2 (TMRx_CC2).
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetCompareCH2 (TMR_TypeDef *TMRx)
	Get compare value (TMRx_CC2) set for output channel 2.
__STATIC_INLINE void	DDL_TMR_OC_SetCompareCH3 (TMR_TypeDef *TMRx, uint32_t CompareValue)
	Set compare value for output channel 3 (TMRx_CC3).
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetCompareCH3 (TMR_TypeDef *TMRx)
	Get compare value (TMRx_CC3) set for output channel 3.
__STATIC_INLINE void	DDL_TMR_OC_SetCompareCH4 (TMR_TypeDef *TMRx, uint32_t CompareValue)
	Set compare value for output channel 4 (TMRx_CC4).
__STATIC_INLINE uint32_t	DDL_TMR_OC_GetCompareCH4 (TMR_TypeDef *TMRx)
	Get compare value (TMRx_CC4) set for output channel 4.
__STATIC_INLINE void	DDL_TMR_IC_Config (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Configuration)
	Configure input channel.
__STATIC_INLINE void	DDL_TMR_IC_SetActiveInput (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICActiveInput)
	Set the active input.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetActiveInput (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the current active input.
__STATIC_INLINE void	DDL_TMR_IC_SetPrescaler (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICPrescaler)
	Set the prescaler of input channel.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetPrescaler (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the current prescaler value acting on an input channel.
__STATIC_INLINE void	DDL_TMR_IC_SetFilter (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICFilter)
	Set the input filter duration.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetFilter (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the input filter duration.
__STATIC_INLINE void	DDL_TMR_IC_SetPolarity (TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICPolarity)
	Set the input channel polarity.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetPolarity (TMR_TypeDef *TMRx, uint32_t Channel)
	Get the current input channel polarity.
__STATIC_INLINE void	DDL_TMR_IC_EnableXORCombination (TMR_TypeDef *TMRx)
	Connect the TMRx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void	DDL_TMR_IC_DisableXORCombination (TMR_TypeDef *TMRx)
	Disconnect the TMRx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t	DDL_TMR_IC_IsEnabledXORCombination (TMR_TypeDef *TMRx)
	Indicates whether the TMRx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetCaptureCH1 (TMR_TypeDef *TMRx)
	Get captured value for input channel 1.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetCaptureCH2 (TMR_TypeDef *TMRx)
	Get captured value for input channel 2.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetCaptureCH3 (TMR_TypeDef *TMRx)
	Get captured value for input channel 3.
__STATIC_INLINE uint32_t	DDL_TMR_IC_GetCaptureCH4 (TMR_TypeDef *TMRx)
	Get captured value for input channel 4.
__STATIC_INLINE void	DDL_TMR_EnableExternalClock (TMR_TypeDef *TMRx)
	Enable external clock mode 2.
__STATIC_INLINE void	DDL_TMR_DisableExternalClock (TMR_TypeDef *TMRx)
	Disable external clock mode 2.
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledExternalClock (TMR_TypeDef *TMRx)
	Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void	DDL_TMR_SetClockSource (TMR_TypeDef *TMRx, uint32_t ClockSource)
	Set the clock source of the counter clock.
__STATIC_INLINE void	DDL_TMR_SetEncoderMode (TMR_TypeDef *TMRx, uint32_t EncoderMode)
	Set the encoder interface mode.
__STATIC_INLINE void	DDL_TMR_SetTriggerOutput (TMR_TypeDef *TMRx, uint32_t TimerSynchronization)
	Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void	DDL_TMR_SetSlaveMode (TMR_TypeDef *TMRx, uint32_t SlaveMode)
	Set the synchronization mode of a slave timer.
__STATIC_INLINE void	DDL_TMR_SetTriggerInput (TMR_TypeDef *TMRx, uint32_t TriggerInput)
	Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void	DDL_TMR_EnableMasterSlaveMode (TMR_TypeDef *TMRx)
	Enable the Master/Slave mode.
__STATIC_INLINE void	DDL_TMR_DisableMasterSlaveMode (TMR_TypeDef *TMRx)
	Disable the Master/Slave mode.
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledMasterSlaveMode (TMR_TypeDef *TMRx)
	Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void	DDL_TMR_ConfigETR (TMR_TypeDef *TMRx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
	Configure the external trigger (ETR) input.
__STATIC_INLINE void	DDL_TMR_EnableBRK (TMR_TypeDef *TMRx)
	Enable the break function.
__STATIC_INLINE void	DDL_TMR_DisableBRK (TMR_TypeDef *TMRx)
	Disable the break function.
__STATIC_INLINE void	DDL_TMR_ConfigBRK (TMR_TypeDef *TMRx, uint32_t BreakPolarity)
	Configure the break input.
__STATIC_INLINE void	DDL_TMR_SetOffStates (TMR_TypeDef *TMRx, uint32_t OffStateIdle, uint32_t OffStateRun)
	Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
__STATIC_INLINE void	DDL_TMR_EnableAutomaticOutput (TMR_TypeDef *TMRx)
	Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void	DDL_TMR_DisableAutomaticOutput (TMR_TypeDef *TMRx)
	Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledAutomaticOutput (TMR_TypeDef *TMRx)
	Indicate whether automatic output is enabled.
__STATIC_INLINE void	DDL_TMR_EnableAllOutputs (TMR_TypeDef *TMRx)
	Enable the outputs (set the MOE bit in TMRx_BDTR register).
__STATIC_INLINE void	DDL_TMR_DisableAllOutputs (TMR_TypeDef *TMRx)
	Disable the outputs (reset the MOE bit in TMRx_BDTR register).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledAllOutputs (TMR_TypeDef *TMRx)
	Indicates whether outputs are enabled.
__STATIC_INLINE void	DDL_TMR_ConfigDMABurst (TMR_TypeDef *TMRx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
	Configures the timer DMA burst feature.
__STATIC_INLINE void	DDL_TMR_ClearFlag_UPDATE (TMR_TypeDef *TMRx)
	Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_UPDATE (TMR_TypeDef *TMRx)
	Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC1 (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC1 (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC2 (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC2 (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC3 (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC3 (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC4 (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC4 (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_COM (TMR_TypeDef *TMRx)
	Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_COM (TMR_TypeDef *TMRx)
	Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_TRIG (TMR_TypeDef *TMRx)
	Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_TRIG (TMR_TypeDef *TMRx)
	Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_BRK (TMR_TypeDef *TMRx)
	Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_BRK (TMR_TypeDef *TMRx)
	Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC1OVR (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC1OVR (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC2OVR (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC2OVR (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC3OVR (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC3OVR (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void	DDL_TMR_ClearFlag_CC4OVR (TMR_TypeDef *TMRx)
	Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t	DDL_TMR_IsActiveFlag_CC4OVR (TMR_TypeDef *TMRx)
	Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void	DDL_TMR_EnableIT_UPDATE (TMR_TypeDef *TMRx)
	Enable update interrupt (UIE).
__STATIC_INLINE void	DDL_TMR_DisableIT_UPDATE (TMR_TypeDef *TMRx)
	Disable update interrupt (UIE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_UPDATE (TMR_TypeDef *TMRx)
	Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_CC1 (TMR_TypeDef *TMRx)
	Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void	DDL_TMR_DisableIT_CC1 (TMR_TypeDef *TMRx)
	Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_CC1 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_CC2 (TMR_TypeDef *TMRx)
	Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void	DDL_TMR_DisableIT_CC2 (TMR_TypeDef *TMRx)
	Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_CC2 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_CC3 (TMR_TypeDef *TMRx)
	Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void	DDL_TMR_DisableIT_CC3 (TMR_TypeDef *TMRx)
	Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_CC3 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_CC4 (TMR_TypeDef *TMRx)
	Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void	DDL_TMR_DisableIT_CC4 (TMR_TypeDef *TMRx)
	Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_CC4 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_COM (TMR_TypeDef *TMRx)
	Enable commutation interrupt (COMIE).
__STATIC_INLINE void	DDL_TMR_DisableIT_COM (TMR_TypeDef *TMRx)
	Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_COM (TMR_TypeDef *TMRx)
	Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_TRIG (TMR_TypeDef *TMRx)
	Enable trigger interrupt (TIE).
__STATIC_INLINE void	DDL_TMR_DisableIT_TRIG (TMR_TypeDef *TMRx)
	Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_TRIG (TMR_TypeDef *TMRx)
	Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableIT_BRK (TMR_TypeDef *TMRx)
	Enable break interrupt (BIE).
__STATIC_INLINE void	DDL_TMR_DisableIT_BRK (TMR_TypeDef *TMRx)
	Disable break interrupt (BIE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledIT_BRK (TMR_TypeDef *TMRx)
	Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_UPDATE (TMR_TypeDef *TMRx)
	Enable update DMA request (UDE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_UPDATE (TMR_TypeDef *TMRx)
	Disable update DMA request (UDE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_UPDATE (TMR_TypeDef *TMRx)
	Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_CC1 (TMR_TypeDef *TMRx)
	Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_CC1 (TMR_TypeDef *TMRx)
	Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_CC1 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_CC2 (TMR_TypeDef *TMRx)
	Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_CC2 (TMR_TypeDef *TMRx)
	Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_CC2 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_CC3 (TMR_TypeDef *TMRx)
	Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_CC3 (TMR_TypeDef *TMRx)
	Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_CC3 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_CC4 (TMR_TypeDef *TMRx)
	Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_CC4 (TMR_TypeDef *TMRx)
	Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_CC4 (TMR_TypeDef *TMRx)
	Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_COM (TMR_TypeDef *TMRx)
	Enable commutation DMA request (COMDE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_COM (TMR_TypeDef *TMRx)
	Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_COM (TMR_TypeDef *TMRx)
	Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void	DDL_TMR_EnableDMAReq_TRIG (TMR_TypeDef *TMRx)
	Enable trigger interrupt (TDE).
__STATIC_INLINE void	DDL_TMR_DisableDMAReq_TRIG (TMR_TypeDef *TMRx)
	Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t	DDL_TMR_IsEnabledDMAReq_TRIG (TMR_TypeDef *TMRx)
	Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_UPDATE (TMR_TypeDef *TMRx)
	Generate an update event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_CC1 (TMR_TypeDef *TMRx)
	Generate Capture/Compare 1 event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_CC2 (TMR_TypeDef *TMRx)
	Generate Capture/Compare 2 event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_CC3 (TMR_TypeDef *TMRx)
	Generate Capture/Compare 3 event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_CC4 (TMR_TypeDef *TMRx)
	Generate Capture/Compare 4 event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_COM (TMR_TypeDef *TMRx)
	Generate commutation event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_TRIG (TMR_TypeDef *TMRx)
	Generate trigger event.
__STATIC_INLINE void	DDL_TMR_GenerateEvent_BRK (TMR_TypeDef *TMRx)
	Generate break event.
ErrorStatus	DDL_TMR_DeInit (TMR_TypeDef *TMRx)
	Set TMRx registers to their reset values.
void	DDL_TMR_StructInit (DDL_TMR_InitTypeDef *TMR_InitStruct)
	Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus	DDL_TMR_Init (TMR_TypeDef *TMRx, DDL_TMR_InitTypeDef *TMR_InitStruct)
	Configure the TMRx time base unit.
void	DDL_TMR_OC_StructInit (DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct)
	Set the fields of the TMRx output channel configuration data structure to their default values.
ErrorStatus	DDL_TMR_OC_Init (TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct)
	Configure the TMRx output channel.
void	DDL_TMR_IC_StructInit (DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct)
	Set the fields of the TMRx input channel configuration data structure to their default values.
ErrorStatus	DDL_TMR_IC_Init (TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_IC_InitTypeDef *TMR_IC_InitStruct)
	Configure the TMRx input channel.
void	DDL_TMR_ENCODER_StructInit (DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct)
	Fills each TMR_EncoderInitStruct field with its default value.
ErrorStatus	DDL_TMR_ENCODER_Init (TMR_TypeDef *TMRx, DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct)
	Configure the encoder interface of the timer instance.
void	DDL_TMR_HALLSENSOR_StructInit (DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct)
	Set the fields of the TMRx Hall sensor interface configuration data structure to their default values.
ErrorStatus	DDL_TMR_HALLSENSOR_Init (TMR_TypeDef *TMRx, DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct)
	Configure the Hall sensor interface of the timer instance.
void	DDL_TMR_BDT_StructInit (DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct)
	Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus	DDL_TMR_BDT_Init (TMR_TypeDef *TMRx, DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct)
	Configure the Break and Dead Time feature of the timer instance.

Variables
static const uint8_t	OFFSET_TAB_CCMRx []
static const uint8_t	SHIFT_TAB_OCxx []
static const uint8_t	SHIFT_TAB_ICxx []
static const uint8_t	SHIFT_TAB_CCxP []
static const uint8_t	SHIFT_TAB_OISx []

Detailed Description

Header file of TMR DDL module.

Attention

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The original code has been modified by Geehy Semiconductor.

Copyright (c) 2016 STMicroelectronics. Copyright (C) 2025 Geehy Semiconductor. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file g32r4xx_ddl_tmr.h.