g32r4xx_ddl_tmr.h

Go to the documentation of this file.

 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef G32R4xx_DDL_TMR_H
#define G32R4xx_DDL_TMR_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx.h"

 
#if defined (TMR1) || defined (TMR2) || defined (TMR3) || defined (TMR4)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static const uint8_t OFFSET_TAB_CCMRx[] =
{
  0x00U,          /* 0: TMRx_CH1  */
  0x00U,          /* 1: TMRx_CH1N */
  0x00U,          /* 2: TMRx_CH2  */
  0x00U,          /* 3: TMRx_CH2N */
  0x04U,          /* 4: TMRx_CH3  */
  0x04U,          /* 5: TMRx_CH3N */
  0x04U           /* 6: TMRx_CH4  */
};
 
static const uint8_t SHIFT_TAB_OCxx[] =
{
  0U,            /* 0: OC1M, OC1FE, OC1PE */
  0U,            /* 1: - NA */
  8U,            /* 2: OC2M, OC2FE, OC2PE */
  0U,            /* 3: - NA */
  0U,            /* 4: OC3M, OC3FE, OC3PE */
  0U,            /* 5: - NA */
  8U             /* 6: OC4M, OC4FE, OC4PE */
};
 
static const uint8_t SHIFT_TAB_ICxx[] =
{
  0U,            /* 0: CC1S, IC1PSC, IC1F */
  0U,            /* 1: - NA */
  8U,            /* 2: CC2S, IC2PSC, IC2F */
  0U,            /* 3: - NA */
  0U,            /* 4: CC3S, IC3PSC, IC3F */
  0U,            /* 5: - NA */
  8U             /* 6: CC4S, IC4PSC, IC4F */
};
 
static const uint8_t SHIFT_TAB_CCxP[] =
{
  0U,            /* 0: CC1P */
  2U,            /* 1: CC1NP */
  4U,            /* 2: CC2P */
  6U,            /* 3: CC2NP */
  8U,            /* 4: CC3P */
  10U,           /* 5: CC3NP */
  12U            /* 6: CC4P */
};
 
static const uint8_t SHIFT_TAB_OISx[] =
{
  0U,            /* 0: OIS1 */
  1U,            /* 1: OIS1N */
  2U,            /* 2: OIS2 */
  3U,            /* 3: OIS2N */
  4U,            /* 4: OIS3 */
  5U,            /* 5: OIS3N */
  6U             /* 6: OIS4 */
};

 
/* Private constants ---------------------------------------------------------*/
/* Mask used to set the TDG[x:0] of the DTG bits of the TMRx_BDTR register */
#define DT_DELAY_1                            ((uint8_t)0x7F)
#define DT_DELAY_2                            ((uint8_t)0x3F)
#define DT_DELAY_3                            ((uint8_t)0x1F)
#define DT_DELAY_4                            ((uint8_t)0x1F)
 
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TMRx_BDTR register */
#define DT_RANGE_1                            ((uint8_t)0x00)
#define DT_RANGE_2                            ((uint8_t)0x80)
#define DT_RANGE_3                            ((uint8_t)0xC0)
#define DT_RANGE_4                            ((uint8_t)0xE0)
 
/* Private macros ------------------------------------------------------------*/
#define TMR_GET_CHANNEL_INDEX(                __CHANNEL__) \
  (((__CHANNEL__) == DDL_TMR_CHANNEL_CH1) ? 0U :\
   ((__CHANNEL__) == DDL_TMR_CHANNEL_CH1N) ? 1U :\
   ((__CHANNEL__) == DDL_TMR_CHANNEL_CH2) ? 2U :\
   ((__CHANNEL__) == DDL_TMR_CHANNEL_CH2N) ? 3U :\
   ((__CHANNEL__) == DDL_TMR_CHANNEL_CH3) ? 4U :\
   ((__CHANNEL__) == DDL_TMR_CHANNEL_CH3N) ? 5U : 6U)

#define TMR_CALC_DTS(__TMRCLK__,              __CKD__)                                                        \
  (((__CKD__) == DDL_TMR_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TMRCLK__))         : \
   ((__CKD__) == DDL_TMR_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TMRCLK__) >> 1U)) : \
   ((uint64_t)1000000000000U/((__TMRCLK__) >> 2U)))

 
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_DDL_DRIVER)

typedef struct
{
  uint16_t Prescaler;         
 
  uint32_t CounterMode;       
 
  uint32_t Autoreload;        
 
  uint32_t ClockDivision;     
 
  uint32_t RepetitionCounter;  
} DDL_TMR_InitTypeDef;

typedef struct
{
  uint32_t OCMode;        
 
  uint32_t OCState;       
 
  uint32_t OCNState;      
 
  uint32_t CompareValue;  
 
  uint32_t OCPolarity;    
 
  uint32_t OCNPolarity;   
 
  uint32_t OCIdleState;   
 
  uint32_t OCNIdleState;  
} DDL_TMR_OC_InitTypeDef;

 
typedef struct
{
 
  uint32_t ICPolarity;    
 
  uint32_t ICActiveInput; 
 
  uint32_t ICPrescaler;   
 
  uint32_t ICFilter;      
} DDL_TMR_IC_InitTypeDef;

typedef struct
{
  uint32_t EncoderMode;     
 
  uint32_t IC1Polarity;     
 
  uint32_t IC1ActiveInput;  
 
  uint32_t IC1Prescaler;    
 
  uint32_t IC1Filter;       
 
  uint32_t IC2Polarity;     
 
  uint32_t IC2ActiveInput;  
 
  uint32_t IC2Prescaler;    
 
  uint32_t IC2Filter;       
 
} DDL_TMR_ENCODER_InitTypeDef;

typedef struct
{
 
  uint32_t IC1Polarity;        
 
  uint32_t IC1Prescaler;       
 
  uint32_t IC1Filter;          
 
  uint32_t CommutationDelay;   
} DDL_TMR_HALLSENSOR_InitTypeDef;

typedef struct
{
  uint32_t OSSRState;            
 
  uint32_t OSSIState;            
 
  uint32_t LockLevel;            
 
  uint8_t DeadTime;              
 
  uint16_t BreakState;           
 
  uint32_t BreakPolarity;        
 
  uint32_t AutomaticOutput;      
} DDL_TMR_BDT_InitTypeDef;

#endif /* USE_FULL_DDL_DRIVER */
 
/* Exported constants --------------------------------------------------------*/

#define DDL_TMR_STS_UIFLG     TMR_STS_UIFLG     
#define DDL_TMR_STS_CC1IFLG   TMR_STS_CC1IFLG   
#define DDL_TMR_STS_CC2IFLG   TMR_STS_CC2IFLG   
#define DDL_TMR_STS_CC3IFLG   TMR_STS_CC3IFLG   
#define DDL_TMR_STS_CC4IFLG   TMR_STS_CC4IFLG   
#define DDL_TMR_STS_COMIFLG   TMR_STS_COMIFLG   
#define DDL_TMR_STS_TRGIFLG   TMR_STS_TRGIFLG   
#define DDL_TMR_STS_BRKIFLG   TMR_STS_BRKIFLG   
#define DDL_TMR_STS_CC1RCFLG  TMR_STS_CC1RCFLG  
#define DDL_TMR_STS_CC2RCFLG  TMR_STS_CC2RCFLG  
#define DDL_TMR_STS_CC3RCFLG  TMR_STS_CC3RCFLG  
#define DDL_TMR_STS_CC4RCFLG  TMR_STS_CC4RCFLG  
 
#if defined(USE_FULL_DDL_DRIVER)
#define DDL_TMR_BREAK_DISABLE  0x00000000U    
#define DDL_TMR_BREAK_ENABLE   TMR_BDT_BRKEN  

#define DDL_TMR_AUTOMATICOUTPUT_DISABLE  0x00000000U   
#define DDL_TMR_AUTOMATICOUTPUT_ENABLE   TMR_BDT_AOEN  
#endif /* USE_FULL_DDL_DRIVER */

#define DDL_TMR_DIEN_UIEN    TMR_DIEN_UIEN    
#define DDL_TMR_DIEN_CC1IEN  TMR_DIEN_CC1IEN  
#define DDL_TMR_DIEN_CC2IEN  TMR_DIEN_CC2IEN  
#define DDL_TMR_DIEN_CC3IEN  TMR_DIEN_CC3IEN  
#define DDL_TMR_DIEN_CC4IEN  TMR_DIEN_CC4IEN  
#define DDL_TMR_DIEN_COMIEN  TMR_DIEN_COMIEN  
#define DDL_TMR_DIEN_TRGIEN  TMR_DIEN_TRGIEN  
#define DDL_TMR_DIEN_BRKIEN  TMR_DIEN_BRKIEN  

#define DDL_TMR_UPDATESOURCE_REGULAR  0x00000000U       
#define DDL_TMR_UPDATESOURCE_COUNTER  TMR_CTRL1_URSSEL  

#define DDL_TMR_ONEPULSEMODE_SINGLE      TMR_CTRL1_SPMEN  
#define DDL_TMR_ONEPULSEMODE_REPETITIVE  0x00000000U      

#define DDL_TMR_COUNTERMODE_UP              0x00000000U         
#define DDL_TMR_COUNTERMODE_DOWN            TMR_CTRL1_CNTDIR    
#define DDL_TMR_COUNTERMODE_CENTER_DOWN     TMR_CTRL1_CAMSEL_0  
#define DDL_TMR_COUNTERMODE_CENTER_UP       TMR_CTRL1_CAMSEL_1  
#define DDL_TMR_COUNTERMODE_CENTER_UP_DOWN  TMR_CTRL1_CAMSEL    

#define DDL_TMR_CLOCKDIVISION_DIV1  0x00000000U         
#define DDL_TMR_CLOCKDIVISION_DIV2  TMR_CTRL1_CLKDIV_0  
#define DDL_TMR_CLOCKDIVISION_DIV4  TMR_CTRL1_CLKDIV_1  

#define DDL_TMR_COUNTERDIRECTION_UP    0x00000000U       
#define DDL_TMR_COUNTERDIRECTION_DOWN  TMR_CTRL1_CNTDIR  

#define DDL_TMR_CCUPDATESOURCE_COMG_ONLY      0x00000000U       
#define DDL_TMR_CCUPDATESOURCE_COMG_AND_TRGI  TMR_CTRL2_CCUSEL  

#define DDL_TMR_CCDMAREQUEST_CC      0x00000000U       
#define DDL_TMR_CCDMAREQUEST_UPDATE  TMR_CTRL2_CCDSEL  

#define DDL_TMR_LOCKLEVEL_OFF  0x00000000U        
#define DDL_TMR_LOCKLEVEL_1    TMR_BDT_LOCKCFG_0  
#define DDL_TMR_LOCKLEVEL_2    TMR_BDT_LOCKCFG_1  
#define DDL_TMR_LOCKLEVEL_3    TMR_BDT_LOCKCFG    

#define DDL_TMR_CHANNEL_CH1   TMR_CCEN_CC1EN   
#define DDL_TMR_CHANNEL_CH1N  TMR_CCEN_CC1NEN  
#define DDL_TMR_CHANNEL_CH2   TMR_CCEN_CC2EN   
#define DDL_TMR_CHANNEL_CH2N  TMR_CCEN_CC2NEN  
#define DDL_TMR_CHANNEL_CH3   TMR_CCEN_CC3EN   
#define DDL_TMR_CHANNEL_CH3N  TMR_CCEN_CC3NEN  
#define DDL_TMR_CHANNEL_CH4   TMR_CCEN_CC4EN   
 
#if defined(USE_FULL_DDL_DRIVER)
#define DDL_TMR_OCSTATE_DISABLE  0x00000000U     
#define DDL_TMR_OCSTATE_ENABLE   TMR_CCEN_CC1EN  
#endif /* USE_FULL_DDL_DRIVER */

#define DDL_TMR_OCMODE_FROZEN           (0x00000000U)                            
#define DDL_TMR_OCMODE_ACTIVE           (TMR_CCM1_OC1MOD_0)                      
#define DDL_TMR_OCMODE_INACTIVE         (TMR_CCM1_OC1MOD_1)                      
#define DDL_TMR_OCMODE_TOGGLE           (TMR_CCM1_OC1MOD_1 | TMR_CCM1_OC1MOD_0)  
#define DDL_TMR_OCMODE_FORCED_INACTIVE  (TMR_CCM1_OC1MOD_2)                      
#define DDL_TMR_OCMODE_FORCED_ACTIVE    (TMR_CCM1_OC1MOD_2 | TMR_CCM1_OC1MOD_0)  
#define DDL_TMR_OCMODE_PWM1             (TMR_CCM1_OC1MOD_2 | TMR_CCM1_OC1MOD_1)  
#define DDL_TMR_OCMODE_PWM2             (TMR_CCM1_OC1MOD)                        

#define DDL_TMR_OCPOLARITY_HIGH  0x00000000U      
#define DDL_TMR_OCPOLARITY_LOW   TMR_CCEN_CC1POL  

#define DDL_TMR_OCIDLESTATE_LOW   0x00000000U       
#define DDL_TMR_OCIDLESTATE_HIGH  TMR_CTRL2_OC1OIS  
#define DDL_TMR_ACTIVEINPUT_DIRECTTI    (TMR_CCM1_CC1SEL_0)  
#define DDL_TMR_ACTIVEINPUT_INDIRECTTI  (TMR_CCM1_CC1SEL_1)  
#define DDL_TMR_ACTIVEINPUT_TRC         (TMR_CCM1_CC1SEL)    
#define DDL_TMR_ICPSC_DIV1  0x00000000U          
#define DDL_TMR_ICPSC_DIV2  (TMR_CCM1_IC1PSC_0)  
#define DDL_TMR_ICPSC_DIV4  (TMR_CCM1_IC1PSC_1)  
#define DDL_TMR_ICPSC_DIV8  (TMR_CCM1_IC1PSC)    

#define DDL_TMR_IC_FILTER_FDIV1      (0x00000000U)                                            
#define DDL_TMR_IC_FILTER_FDIV1_N2   (TMR_CCM1_IC1F_0)                                        
#define DDL_TMR_IC_FILTER_FDIV1_N4   (TMR_CCM1_IC1F_1)                                        
#define DDL_TMR_IC_FILTER_FDIV1_N8   ((TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))                    
#define DDL_TMR_IC_FILTER_FDIV2_N6   (TMR_CCM1_IC1F_2)                                        
#define DDL_TMR_IC_FILTER_FDIV2_N8   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_0))                    
#define DDL_TMR_IC_FILTER_FDIV4_N6   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1))                    
#define DDL_TMR_IC_FILTER_FDIV4_N8   ((TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))  
#define DDL_TMR_IC_FILTER_FDIV8_N6   (TMR_CCM1_IC1F_3)                                        
#define DDL_TMR_IC_FILTER_FDIV8_N8   ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_0))                    
#define DDL_TMR_IC_FILTER_FDIV16_N5  ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_1))                    
#define DDL_TMR_IC_FILTER_FDIV16_N6  ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_1 | TMR_CCM1_IC1F_0))  
#define DDL_TMR_IC_FILTER_FDIV16_N8  ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2))                    
#define DDL_TMR_IC_FILTER_FDIV32_N5  ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_0))  
#define DDL_TMR_IC_FILTER_FDIV32_N6  ((TMR_CCM1_IC1F_3 | TMR_CCM1_IC1F_2 | TMR_CCM1_IC1F_1))  
#define DDL_TMR_IC_FILTER_FDIV32_N8  (TMR_CCM1_IC1F)                                          

#define DDL_TMR_IC_POLARITY_RISING    0x00000000U                           
#define DDL_TMR_IC_POLARITY_FALLING   TMR_CCEN_CC1POL                       
#define DDL_TMR_IC_POLARITY_BOTHEDGE  (TMR_CCEN_CC1POL | TMR_CCEN_CC1NPOL)  

#define DDL_TMR_CLOCKSOURCE_INTERNAL   0x00000000U        
#define DDL_TMR_CLOCKSOURCE_EXT_MODE1  TMR_SMCTRL_SMFSEL  
#define DDL_TMR_CLOCKSOURCE_EXT_MODE2  TMR_SMCTRL_ECEN    

#define DDL_TMR_ENCODERMODE_X2_TI1   (TMR_SMCTRL_SMFSEL_0)                        
#define DDL_TMR_ENCODERMODE_X2_TI2   (TMR_SMCTRL_SMFSEL_1)                        
#define DDL_TMR_ENCODERMODE_X4_TI12  (TMR_SMCTRL_SMFSEL_1 | TMR_SMCTRL_SMFSEL_0)  

#define DDL_TMR_TRGO_RESET   (0x00000000U)                            
#define DDL_TMR_TRGO_ENABLE  (TMR_CTRL2_MMSEL_0)                      
#define DDL_TMR_TRGO_UPDATE  (TMR_CTRL2_MMSEL_1)                      
#define DDL_TMR_TRGO_CC1IF   (TMR_CTRL2_MMSEL_1 | TMR_CTRL2_MMSEL_0)  
#define DDL_TMR_TRGO_OC1REF  (TMR_CTRL2_MMSEL_2)                      
#define DDL_TMR_TRGO_OC2REF  (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_0)  
#define DDL_TMR_TRGO_OC3REF  (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_1)  
#define DDL_TMR_TRGO_OC4REF  (TMR_CTRL2_MMSEL)                        

#define DDL_TMR_SLAVEMODE_DISABLED  (0x00000000U)                                
#define DDL_TMR_SLAVEMODE_RESET     (TMR_SMCTRL_SMFSEL_2)                        
#define DDL_TMR_SLAVEMODE_GATED     (TMR_SMCTRL_SMFSEL_2 | TMR_SMCTRL_SMFSEL_0)  
#define DDL_TMR_SLAVEMODE_TRIGGER   (TMR_SMCTRL_SMFSEL_2 | TMR_SMCTRL_SMFSEL_1)  

#define DDL_TMR_TS_ITR0     (0x00000000U)                                
#define DDL_TMR_TS_ITR1     (TMR_SMCTRL_TRGSEL_0)                        
#define DDL_TMR_TS_ITR2     (TMR_SMCTRL_TRGSEL_1)                        
#define DDL_TMR_TS_ITR3     (TMR_SMCTRL_TRGSEL_0 | TMR_SMCTRL_TRGSEL_1)  
#define DDL_TMR_TS_TI1F_ED  (TMR_SMCTRL_TRGSEL_2)                        
#define DDL_TMR_TS_TI1FP1   (TMR_SMCTRL_TRGSEL_2 | TMR_SMCTRL_TRGSEL_0)  
#define DDL_TMR_TS_TI2FP2   (TMR_SMCTRL_TRGSEL_2 | TMR_SMCTRL_TRGSEL_1)  
#define DDL_TMR_TS_ETRF     (TMR_SMCTRL_TRGSEL)                          

#define DDL_TMR_ETR_POLARITY_NONINVERTED  0x00000000U       
#define DDL_TMR_ETR_POLARITY_INVERTED     TMR_SMCTRL_ETPOL  

#define DDL_TMR_ETR_PRESCALER_DIV1  0x00000000U          
#define DDL_TMR_ETR_PRESCALER_DIV2  TMR_SMCTRL_ETPCFG_0  
#define DDL_TMR_ETR_PRESCALER_DIV4  TMR_SMCTRL_ETPCFG_1  
#define DDL_TMR_ETR_PRESCALER_DIV8  TMR_SMCTRL_ETPCFG    

#define DDL_TMR_ETR_FILTER_FDIV1      (0x00000000U)                                                      
#define DDL_TMR_ETR_FILTER_FDIV1_N2   (TMR_SMCTRL_ETFCFG_0)                                              
#define DDL_TMR_ETR_FILTER_FDIV1_N4   (TMR_SMCTRL_ETFCFG_1)                                              
#define DDL_TMR_ETR_FILTER_FDIV1_N8   (TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)                        
#define DDL_TMR_ETR_FILTER_FDIV2_N6   (TMR_SMCTRL_ETFCFG_2)                                              
#define DDL_TMR_ETR_FILTER_FDIV2_N8   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0)                        
#define DDL_TMR_ETR_FILTER_FDIV4_N6   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1)                        
#define DDL_TMR_ETR_FILTER_FDIV4_N8   (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)  
#define DDL_TMR_ETR_FILTER_FDIV8_N6   (TMR_SMCTRL_ETFCFG_3)                                              
#define DDL_TMR_ETR_FILTER_FDIV8_N8   (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_0)                        
#define DDL_TMR_ETR_FILTER_FDIV16_N5  (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1)                        
#define DDL_TMR_ETR_FILTER_FDIV16_N6  (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0)  
#define DDL_TMR_ETR_FILTER_FDIV16_N8  (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2)                        
#define DDL_TMR_ETR_FILTER_FDIV32_N5  (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0)  
#define DDL_TMR_ETR_FILTER_FDIV32_N6  (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1)  
#define DDL_TMR_ETR_FILTER_FDIV32_N8  (TMR_SMCTRL_ETFCFG)                                                

#define DDL_TMR_BREAK_POLARITY_LOW   0x00000000U     
#define DDL_TMR_BREAK_POLARITY_HIGH  TMR_BDT_BRKPOL  

#define DDL_TMR_OSSI_DISABLE  0x00000000U   
#define DDL_TMR_OSSI_ENABLE   TMR_BDT_IMOS  

#define DDL_TMR_OSSR_DISABLE  0x00000000U   
#define DDL_TMR_OSSR_ENABLE   TMR_BDT_RMOS  

#define DDL_TMR_DMABURST_BASEADDR_CTRL1    (0x00000000U)                                                                        
#define DDL_TMR_DMABURST_BASEADDR_CTRL2    (TMR_DCTRL_DBADDR_0)                                                                 
#define DDL_TMR_DMABURST_BASEADDR_SMCTRL   (TMR_DCTRL_DBADDR_1)                                                                 
#define DDL_TMR_DMABURST_BASEADDR_DIEN     (TMR_DCTRL_DBADDR_1 |  TMR_DCTRL_DBADDR_0)                                           
#define DDL_TMR_DMABURST_BASEADDR_STS      (TMR_DCTRL_DBADDR_2)                                                                 
#define DDL_TMR_DMABURST_BASEADDR_CEG      (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)                                            
#define DDL_TMR_DMABURST_BASEADDR_CCM1     (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)                                            
#define DDL_TMR_DMABURST_BASEADDR_CCM2     (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)                       
#define DDL_TMR_DMABURST_BASEADDR_CCEN     (TMR_DCTRL_DBADDR_3)                                                                 
#define DDL_TMR_DMABURST_BASEADDR_CNT      (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_0)                                            
#define DDL_TMR_DMABURST_BASEADDR_PSC      (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1)                                            
#define DDL_TMR_DMABURST_BASEADDR_AUTORLD  (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)                       
#define DDL_TMR_DMABURST_BASEADDR_REPCNT   (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2)                                            
#define DDL_TMR_DMABURST_BASEADDR_CC1      (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)                       
#define DDL_TMR_DMABURST_BASEADDR_CC2      (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)                       
#define DDL_TMR_DMABURST_BASEADDR_CC3      (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)  
#define DDL_TMR_DMABURST_BASEADDR_CC4      (TMR_DCTRL_DBADDR_4)                                                                 
#define DDL_TMR_DMABURST_BASEADDR_BDT      (TMR_DCTRL_DBADDR_4 | TMR_DCTRL_DBADDR_0)                                            

#define DDL_TMR_DMABURST_LENGTH_1TRANSFER    (0x00000000U)                                                                    
#define DDL_TMR_DMABURST_LENGTH_2TRANSFERS   (TMR_DCTRL_DBLEN_0)                                                              
#define DDL_TMR_DMABURST_LENGTH_3TRANSFERS   (TMR_DCTRL_DBLEN_1)                                                              
#define DDL_TMR_DMABURST_LENGTH_4TRANSFERS   (TMR_DCTRL_DBLEN_1 |  TMR_DCTRL_DBLEN_0)                                         
#define DDL_TMR_DMABURST_LENGTH_5TRANSFERS   (TMR_DCTRL_DBLEN_2)                                                              
#define DDL_TMR_DMABURST_LENGTH_6TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)                                          
#define DDL_TMR_DMABURST_LENGTH_7TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)                                          
#define DDL_TMR_DMABURST_LENGTH_8TRANSFERS   (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)                      
#define DDL_TMR_DMABURST_LENGTH_9TRANSFERS   (TMR_DCTRL_DBLEN_3)                                                              
#define DDL_TMR_DMABURST_LENGTH_10TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_0)                                          
#define DDL_TMR_DMABURST_LENGTH_11TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1)                                          
#define DDL_TMR_DMABURST_LENGTH_12TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)                      
#define DDL_TMR_DMABURST_LENGTH_13TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2)                                          
#define DDL_TMR_DMABURST_LENGTH_14TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)                      
#define DDL_TMR_DMABURST_LENGTH_15TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)                      
#define DDL_TMR_DMABURST_LENGTH_16TRANSFERS  (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)  
#define DDL_TMR_DMABURST_LENGTH_17TRANSFERS  (TMR_DCTRL_DBLEN_4)                                                              
#define DDL_TMR_DMABURST_LENGTH_18TRANSFERS  (TMR_DCTRL_DBLEN_4 |  TMR_DCTRL_DBLEN_0)                                         

 
/* Exported macro ------------------------------------------------------------*/

#define DDL_TMR_WriteReg(__INSTANCE__,  __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

#define DDL_TMR_ReadReg(__INSTANCE__,  __REG__) READ_REG((__INSTANCE__)->__REG__)


#define __DDL_TMR_CALC_DEADTMRE(__TMRCLK__,   __CKD__, __DT__)  \
  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TMR_CALC_DTS((__TMRCLK__), (__CKD__))))    ?  \
    (uint8_t)(((uint64_t)((__DT__)*1000U) / TMR_CALC_DTS((__TMRCLK__), (__CKD__)))  & DT_DELAY_1) :      \
    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TMR_CALC_DTS((__TMRCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TMR_CALC_DTS((__TMRCLK__),   \
                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TMR_CALC_DTS((__TMRCLK__), (__CKD__))))  ?  \
    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TMR_CALC_DTS((__TMRCLK__),  \
                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TMR_CALC_DTS((__TMRCLK__), (__CKD__)))) ?  \
    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TMR_CALC_DTS((__TMRCLK__),  \
                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
    0U)

#define __DDL_TMR_CALC_PSC(__TMRCLK__,        __CNTCLK__)   \
  (((__TMRCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TMRCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)

#define __DDL_TMR_CALC_ARR(__TMRCLK__,        __PSC__, __FREQ__) \
  ((((__TMRCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TMRCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

#define __DDL_TMR_CALC_DELAY(__TMRCLK__,      __PSC__, __DELAY__)  \
  ((uint32_t)(((uint64_t)(__TMRCLK__) * (uint64_t)(__DELAY__)) \
              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

#define __DDL_TMR_CALC_PULSE(__TMRCLK__,      __PSC__, __DELAY__, __PULSE__)  \
  ((uint32_t)(__DDL_TMR_CALC_DELAY((__TMRCLK__), (__PSC__), (__PULSE__)) \
              + __DDL_TMR_CALC_DELAY((__TMRCLK__), (__PSC__), (__DELAY__))))

#define __DDL_TMR_GET_ICPSC_RATIO(__ICPSC__)  \
  ((uint32_t)(0x01U << (((__ICPSC__)) >> TMR_CCM1_IC1PSC_Pos)))


 
/* Exported functions --------------------------------------------------------*/

__STATIC_INLINE void DDL_TMR_EnableCounter(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CTRL1, TMR_CTRL1_CNTEN);
}

__STATIC_INLINE void DDL_TMR_DisableCounter(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->CTRL1, TMR_CTRL1_CNTEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledCounter(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->CTRL1, TMR_CTRL1_CNTEN) == (TMR_CTRL1_CNTEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableUpdateEvent(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->CTRL1, TMR_CTRL1_UD);
}

__STATIC_INLINE void DDL_TMR_DisableUpdateEvent(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CTRL1, TMR_CTRL1_UD);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledUpdateEvent(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->CTRL1, TMR_CTRL1_UD) == TMR_CTRL1_UD) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_SetUpdateSource(TMR_TypeDef *TMRx, uint32_t UpdateSource)
{
  MODIFY_REG(TMRx->CTRL1, TMR_CTRL1_URSSEL, UpdateSource);
}

__STATIC_INLINE uint32_t DDL_TMR_GetUpdateSource(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_URSSEL));
}

__STATIC_INLINE void DDL_TMR_SetOnePulseMode(TMR_TypeDef *TMRx, uint32_t OnePulseMode)
{
  MODIFY_REG(TMRx->CTRL1, TMR_CTRL1_SPMEN, OnePulseMode);
}

__STATIC_INLINE uint32_t DDL_TMR_GetOnePulseMode(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_SPMEN));
}

__STATIC_INLINE void DDL_TMR_SetCounterMode(TMR_TypeDef *TMRx, uint32_t CounterMode)
{
  MODIFY_REG(TMRx->CTRL1, (TMR_CTRL1_CNTDIR | TMR_CTRL1_CAMSEL), CounterMode);
}

__STATIC_INLINE uint32_t DDL_TMR_GetCounterMode(TMR_TypeDef *TMRx)
{
  uint32_t counter_mode;
 
  counter_mode = (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_CAMSEL));
 
  if (counter_mode == 0U)
  {
    counter_mode = (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_CNTDIR));
  }
 
  return counter_mode;
}

__STATIC_INLINE void DDL_TMR_EnableARRPreload(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CTRL1, TMR_CTRL1_ARPEN);
}

__STATIC_INLINE void DDL_TMR_DisableARRPreload(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->CTRL1, TMR_CTRL1_ARPEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledARRPreload(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->CTRL1, TMR_CTRL1_ARPEN) == (TMR_CTRL1_ARPEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_SetClockDivision(TMR_TypeDef *TMRx, uint32_t ClockDivision)
{
  MODIFY_REG(TMRx->CTRL1, TMR_CTRL1_CLKDIV, ClockDivision);
}

__STATIC_INLINE uint32_t DDL_TMR_GetClockDivision(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_CLKDIV));
}

__STATIC_INLINE void DDL_TMR_SetCounter(TMR_TypeDef *TMRx, uint32_t Counter)
{
  WRITE_REG(TMRx->CNT, Counter);
}

__STATIC_INLINE uint32_t DDL_TMR_GetCounter(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CNT));
}

__STATIC_INLINE void DDL_TMR_SetDirection(TMR_TypeDef *TMRx, uint32_t Direction)
{
  MODIFY_REG(TMRx->CTRL1, TMR_CTRL1_CNTDIR, Direction);
}

__STATIC_INLINE uint32_t DDL_TMR_GetDirection(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL1, TMR_CTRL1_CNTDIR));
}

__STATIC_INLINE void DDL_TMR_SetPrescaler(TMR_TypeDef *TMRx, uint32_t Prescaler)
{
  WRITE_REG(TMRx->PSC, Prescaler);
}

__STATIC_INLINE uint32_t DDL_TMR_GetPrescaler(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->PSC));
}

__STATIC_INLINE void DDL_TMR_SetAutoReload(TMR_TypeDef *TMRx, uint32_t AutoReload)
{
  WRITE_REG(TMRx->AUTORLD, AutoReload);
}

__STATIC_INLINE uint32_t DDL_TMR_GetAutoReload(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->AUTORLD));
}

__STATIC_INLINE void DDL_TMR_SetRepetitionCounter(TMR_TypeDef *TMRx, uint32_t RepetitionCounter)
{
  WRITE_REG(TMRx->REPCNT, RepetitionCounter);
}

__STATIC_INLINE uint32_t DDL_TMR_GetRepetitionCounter(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->REPCNT));
}


__STATIC_INLINE void DDL_TMR_CC_EnablePreload(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CTRL2, TMR_CTRL2_CCPEN);
}

__STATIC_INLINE void DDL_TMR_CC_DisablePreload(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->CTRL2, TMR_CTRL2_CCPEN);
}

__STATIC_INLINE uint32_t DDL_TMR_CC_IsEnabledPreload(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->CTRL2, TMR_CTRL2_CCPEN) == (TMR_CTRL2_CCPEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_CC_SetUpdate(TMR_TypeDef *TMRx, uint32_t CCUpdateSource)
{
  MODIFY_REG(TMRx->CTRL2, TMR_CTRL2_CCUSEL, CCUpdateSource);
}

__STATIC_INLINE uint32_t DDL_TMR_CC_GetUpdate(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL2, TMR_CTRL2_CCUSEL));
}

__STATIC_INLINE void DDL_TMR_CC_SetDMAReqTrigger(TMR_TypeDef *TMRx, uint32_t DMAReqTrigger)
{
  MODIFY_REG(TMRx->CTRL2, TMR_CTRL2_CCDSEL, DMAReqTrigger);
}

__STATIC_INLINE uint32_t DDL_TMR_CC_GetDMAReqTrigger(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_BIT(TMRx->CTRL2, TMR_CTRL2_CCDSEL));
}

__STATIC_INLINE void DDL_TMR_CC_SetLockLevel(TMR_TypeDef *TMRx, uint32_t LockLevel)
{
  MODIFY_REG(TMRx->BDT, TMR_BDT_LOCKCFG, LockLevel);
}

__STATIC_INLINE void DDL_TMR_CC_EnableChannel(TMR_TypeDef *TMRx, uint32_t Channels)
{
  SET_BIT(TMRx->CCEN, Channels);
}

__STATIC_INLINE void DDL_TMR_CC_DisableChannel(TMR_TypeDef *TMRx, uint32_t Channels)
{
  CLEAR_BIT(TMRx->CCEN, Channels);
}

__STATIC_INLINE uint32_t DDL_TMR_CC_IsEnabledChannel(TMR_TypeDef *TMRx, uint32_t Channels)
{
  return ((READ_BIT(TMRx->CCEN, Channels) == (Channels)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_TMR_OC_ConfigOutput(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Configuration)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  CLEAR_BIT(*pReg, (TMR_CCM1_CC1SEL << SHIFT_TAB_OCxx[iChannel]));
  MODIFY_REG(TMRx->CCEN, (TMR_CCEN_CC1POL << SHIFT_TAB_CCxP[iChannel]),
             (Configuration & TMR_CCEN_CC1POL) << SHIFT_TAB_CCxP[iChannel]);
  MODIFY_REG(TMRx->CTRL2, (TMR_CTRL2_OC1OIS << SHIFT_TAB_OISx[iChannel]),
             (Configuration & TMR_CTRL2_OC1OIS) << SHIFT_TAB_OISx[iChannel]);
}

__STATIC_INLINE void DDL_TMR_OC_SetMode(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Mode)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  MODIFY_REG(*pReg, ((TMR_CCM1_OC1MOD  | TMR_CCM1_CC1SEL) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetMode(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  return (READ_BIT(*pReg, ((TMR_CCM1_OC1MOD | TMR_CCM1_CC1SEL) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}

__STATIC_INLINE void DDL_TMR_OC_SetPolarity(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Polarity)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  MODIFY_REG(TMRx->CCEN, (TMR_CCEN_CC1POL << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetPolarity(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  return (READ_BIT(TMRx->CCEN, (TMR_CCEN_CC1POL << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}

__STATIC_INLINE void DDL_TMR_OC_SetIdleState(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t IdleState)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  MODIFY_REG(TMRx->CTRL2, (TMR_CTRL2_OC1OIS << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetIdleState(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  return (READ_BIT(TMRx->CTRL2, (TMR_CTRL2_OC1OIS << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}

__STATIC_INLINE void DDL_TMR_OC_EnableFast(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  SET_BIT(*pReg, (TMR_CCM1_OC1FEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_OC_DisableFast(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  CLEAR_BIT(*pReg, (TMR_CCM1_OC1FEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE uint32_t DDL_TMR_OC_IsEnabledFast(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = TMR_CCM1_OC1FEN << SHIFT_TAB_OCxx[iChannel];
  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_OC_EnablePreload(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  SET_BIT(*pReg, (TMR_CCM1_OC1PEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_OC_DisablePreload(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  CLEAR_BIT(*pReg, (TMR_CCM1_OC1PEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE uint32_t DDL_TMR_OC_IsEnabledPreload(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = TMR_CCM1_OC1PEN << SHIFT_TAB_OCxx[iChannel];
  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_OC_EnableClear(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  SET_BIT(*pReg, (TMR_CCM1_OC1CEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_OC_DisableClear(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  CLEAR_BIT(*pReg, (TMR_CCM1_OC1CEN << SHIFT_TAB_OCxx[iChannel]));
}

__STATIC_INLINE uint32_t DDL_TMR_OC_IsEnabledClear(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = TMR_CCM1_OC1CEN << SHIFT_TAB_OCxx[iChannel];
  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_OC_SetDeadTime(TMR_TypeDef *TMRx, uint32_t DeadTime)
{
  MODIFY_REG(TMRx->BDT, TMR_BDT_DTS, DeadTime);
}

__STATIC_INLINE void DDL_TMR_OC_SetCompareCH1(TMR_TypeDef *TMRx, uint32_t CompareValue)
{
  WRITE_REG(TMRx->CC1, CompareValue);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetCompareCH1(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC1));
}

__STATIC_INLINE void DDL_TMR_OC_SetCompareCH2(TMR_TypeDef *TMRx, uint32_t CompareValue)
{
  WRITE_REG(TMRx->CC2, CompareValue);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetCompareCH2(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC2));
}

__STATIC_INLINE void DDL_TMR_OC_SetCompareCH3(TMR_TypeDef *TMRx, uint32_t CompareValue)
{
  WRITE_REG(TMRx->CC3, CompareValue);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetCompareCH3(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC3));
}

__STATIC_INLINE void DDL_TMR_OC_SetCompareCH4(TMR_TypeDef *TMRx, uint32_t CompareValue)
{
  WRITE_REG(TMRx->CC4, CompareValue);
}

__STATIC_INLINE uint32_t DDL_TMR_OC_GetCompareCH4(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC4));
}


__STATIC_INLINE void DDL_TMR_IC_Config(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t Configuration)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  MODIFY_REG(*pReg, ((TMR_CCM1_IC1F | TMR_CCM1_IC1PSC | TMR_CCM1_CC1SEL) << SHIFT_TAB_ICxx[iChannel]),
             ((Configuration >> 16U) & (TMR_CCM1_IC1F | TMR_CCM1_IC1PSC | TMR_CCM1_CC1SEL))                \
             << SHIFT_TAB_ICxx[iChannel]);
  MODIFY_REG(TMRx->CCEN, ((TMR_CCEN_CC1NPOL | TMR_CCEN_CC1POL) << SHIFT_TAB_CCxP[iChannel]),
             (Configuration & (TMR_CCEN_CC1NPOL | TMR_CCEN_CC1POL)) << SHIFT_TAB_CCxP[iChannel]);
}

__STATIC_INLINE void DDL_TMR_IC_SetActiveInput(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICActiveInput)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  MODIFY_REG(*pReg, ((TMR_CCM1_CC1SEL) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput) << SHIFT_TAB_ICxx[iChannel]);
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetActiveInput(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((READ_BIT(*pReg, ((TMR_CCM1_CC1SEL) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_IC_SetPrescaler(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICPrescaler)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  MODIFY_REG(*pReg, ((TMR_CCM1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), ((ICPrescaler) << SHIFT_TAB_ICxx[iChannel]));
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetPrescaler(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((READ_BIT(*pReg, ((TMR_CCM1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_IC_SetFilter(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICFilter)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  MODIFY_REG(*pReg, ((TMR_CCM1_IC1F) << SHIFT_TAB_ICxx[iChannel]), ((ICFilter) << SHIFT_TAB_ICxx[iChannel]));
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetFilter(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TMRx->CCM1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((READ_BIT(*pReg, ((TMR_CCM1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]));
}

__STATIC_INLINE void DDL_TMR_IC_SetPolarity(TMR_TypeDef *TMRx, uint32_t Channel, uint32_t ICPolarity)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  MODIFY_REG(TMRx->CCEN, ((TMR_CCEN_CC1NPOL | TMR_CCEN_CC1POL) << SHIFT_TAB_CCxP[iChannel]),
             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetPolarity(TMR_TypeDef *TMRx, uint32_t Channel)
{
  uint8_t iChannel = TMR_GET_CHANNEL_INDEX(Channel);
  return (READ_BIT(TMRx->CCEN, ((TMR_CCEN_CC1NPOL | TMR_CCEN_CC1POL) << SHIFT_TAB_CCxP[iChannel])) >>
          SHIFT_TAB_CCxP[iChannel]);
}

__STATIC_INLINE void DDL_TMR_IC_EnableXORCombination(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CTRL2, TMR_CTRL2_TI1SEL);
}

__STATIC_INLINE void DDL_TMR_IC_DisableXORCombination(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->CTRL2, TMR_CTRL2_TI1SEL);
}

__STATIC_INLINE uint32_t DDL_TMR_IC_IsEnabledXORCombination(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->CTRL2, TMR_CTRL2_TI1SEL) == (TMR_CTRL2_TI1SEL)) ? 1UL : 0UL);
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetCaptureCH1(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC1));
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetCaptureCH2(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC2));
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetCaptureCH3(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC3));
}

__STATIC_INLINE uint32_t DDL_TMR_IC_GetCaptureCH4(TMR_TypeDef *TMRx)
{
  return (uint32_t)(READ_REG(TMRx->CC4));
}


__STATIC_INLINE void DDL_TMR_EnableExternalClock(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->SMCTRL, TMR_SMCTRL_ECEN);
}

__STATIC_INLINE void DDL_TMR_DisableExternalClock(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->SMCTRL, TMR_SMCTRL_ECEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledExternalClock(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->SMCTRL, TMR_SMCTRL_ECEN) == (TMR_SMCTRL_ECEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_SetClockSource(TMR_TypeDef *TMRx, uint32_t ClockSource)
{
  MODIFY_REG(TMRx->SMCTRL, TMR_SMCTRL_SMFSEL | TMR_SMCTRL_ECEN, ClockSource);
}

__STATIC_INLINE void DDL_TMR_SetEncoderMode(TMR_TypeDef *TMRx, uint32_t EncoderMode)
{
  MODIFY_REG(TMRx->SMCTRL, TMR_SMCTRL_SMFSEL, EncoderMode);
}


__STATIC_INLINE void DDL_TMR_SetTriggerOutput(TMR_TypeDef *TMRx, uint32_t TimerSynchronization)
{
  MODIFY_REG(TMRx->CTRL2, TMR_CTRL2_MMSEL, TimerSynchronization);
}

__STATIC_INLINE void DDL_TMR_SetSlaveMode(TMR_TypeDef *TMRx, uint32_t SlaveMode)
{
  MODIFY_REG(TMRx->SMCTRL, TMR_SMCTRL_SMFSEL, SlaveMode);
}

__STATIC_INLINE void DDL_TMR_SetTriggerInput(TMR_TypeDef *TMRx, uint32_t TriggerInput)
{
  MODIFY_REG(TMRx->SMCTRL, TMR_SMCTRL_TRGSEL, TriggerInput);
}

__STATIC_INLINE void DDL_TMR_EnableMasterSlaveMode(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->SMCTRL, TMR_SMCTRL_MSMEN);
}

__STATIC_INLINE void DDL_TMR_DisableMasterSlaveMode(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->SMCTRL, TMR_SMCTRL_MSMEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledMasterSlaveMode(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->SMCTRL, TMR_SMCTRL_MSMEN) == (TMR_SMCTRL_MSMEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ConfigETR(TMR_TypeDef *TMRx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
{
  MODIFY_REG(TMRx->SMCTRL, TMR_SMCTRL_ETPOL | TMR_SMCTRL_ETPCFG | TMR_SMCTRL_ETFCFG, ETRPolarity | ETRPrescaler | ETRFilter);
}


__STATIC_INLINE void DDL_TMR_EnableBRK(TMR_TypeDef *TMRx)
{
  __IO uint32_t tmpreg;
  SET_BIT(TMRx->BDT, TMR_BDT_BRKEN);
  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
  tmpreg = READ_REG(TMRx->BDT);
  (void)(tmpreg);
}

__STATIC_INLINE void DDL_TMR_DisableBRK(TMR_TypeDef *TMRx)
{
  __IO uint32_t tmpreg;
  CLEAR_BIT(TMRx->BDT, TMR_BDT_BRKEN);
  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
  tmpreg = READ_REG(TMRx->BDT);
  (void)(tmpreg);
}

__STATIC_INLINE void DDL_TMR_ConfigBRK(TMR_TypeDef *TMRx, uint32_t BreakPolarity)
{
  __IO uint32_t tmpreg;
  MODIFY_REG(TMRx->BDT, TMR_BDT_BRKPOL, BreakPolarity);
  /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
  tmpreg = READ_REG(TMRx->BDT);
  (void)(tmpreg);
}

__STATIC_INLINE void DDL_TMR_SetOffStates(TMR_TypeDef *TMRx, uint32_t OffStateIdle, uint32_t OffStateRun)
{
  MODIFY_REG(TMRx->BDT, TMR_BDT_IMOS | TMR_BDT_RMOS, OffStateIdle | OffStateRun);
}

__STATIC_INLINE void DDL_TMR_EnableAutomaticOutput(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->BDT, TMR_BDT_AOEN);
}

__STATIC_INLINE void DDL_TMR_DisableAutomaticOutput(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->BDT, TMR_BDT_AOEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledAutomaticOutput(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->BDT, TMR_BDT_AOEN) == (TMR_BDT_AOEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableAllOutputs(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->BDT, TMR_BDT_MOEN);
}

__STATIC_INLINE void DDL_TMR_DisableAllOutputs(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->BDT, TMR_BDT_MOEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledAllOutputs(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->BDT, TMR_BDT_MOEN) == (TMR_BDT_MOEN)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_TMR_ConfigDMABurst(TMR_TypeDef *TMRx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
  MODIFY_REG(TMRx->DCTRL, (TMR_DCTRL_DBLEN | TMR_DCTRL_DBADDR), (DMABurstBaseAddress | DMABurstLength));
}


__STATIC_INLINE void DDL_TMR_ClearFlag_UPDATE(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_UIFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_UPDATE(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_UIFLG) == (TMR_STS_UIFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC1(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC1IFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC1(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC1IFLG) == (TMR_STS_CC1IFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC2(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC2IFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC2(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC2IFLG) == (TMR_STS_CC2IFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC3(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC3IFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC3(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC3IFLG) == (TMR_STS_CC3IFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC4(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC4IFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC4(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC4IFLG) == (TMR_STS_CC4IFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_COM(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_COMIFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_COM(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_COMIFLG) == (TMR_STS_COMIFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_TRIG(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_TRGIFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_TRIG(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_TRGIFLG) == (TMR_STS_TRGIFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_BRK(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_BRKIFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_BRK(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_BRKIFLG) == (TMR_STS_BRKIFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC1OVR(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC1RCFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC1OVR(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC1RCFLG) == (TMR_STS_CC1RCFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC2OVR(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC2RCFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC2OVR(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC2RCFLG) == (TMR_STS_CC2RCFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC3OVR(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC3RCFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC3OVR(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC3RCFLG) == (TMR_STS_CC3RCFLG)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_ClearFlag_CC4OVR(TMR_TypeDef *TMRx)
{
  WRITE_REG(TMRx->STS, ~(TMR_STS_CC4RCFLG));
}

__STATIC_INLINE uint32_t DDL_TMR_IsActiveFlag_CC4OVR(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->STS, TMR_STS_CC4RCFLG) == (TMR_STS_CC4RCFLG)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_TMR_EnableIT_UPDATE(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_UIEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_UPDATE(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_UIEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_UPDATE(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_UIEN) == (TMR_DIEN_UIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_CC1(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC1IEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_CC1(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC1IEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_CC1(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC1IEN) == (TMR_DIEN_CC1IEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_CC2(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC2IEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_CC2(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC2IEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_CC2(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC2IEN) == (TMR_DIEN_CC2IEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_CC3(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC3IEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_CC3(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC3IEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_CC3(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC3IEN) == (TMR_DIEN_CC3IEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_CC4(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC4IEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_CC4(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC4IEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_CC4(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC4IEN) == (TMR_DIEN_CC4IEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_COM(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_COMIEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_COM(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_COMIEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_COM(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_COMIEN) == (TMR_DIEN_COMIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_TRIG(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_TRGIEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_TRIG(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_TRGIEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_TRIG(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_TRGIEN) == (TMR_DIEN_TRGIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableIT_BRK(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_BRKIEN);
}

__STATIC_INLINE void DDL_TMR_DisableIT_BRK(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_BRKIEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledIT_BRK(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_BRKIEN) == (TMR_DIEN_BRKIEN)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_TMR_EnableDMAReq_UPDATE(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_UDIEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_UPDATE(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_UDIEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_UPDATE(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_UDIEN) == (TMR_DIEN_UDIEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_CC1(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC1DEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_CC1(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC1DEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_CC1(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC1DEN) == (TMR_DIEN_CC1DEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_CC2(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC2DEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_CC2(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC2DEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_CC2(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC2DEN) == (TMR_DIEN_CC2DEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_CC3(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC3DEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_CC3(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC3DEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_CC3(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC3DEN) == (TMR_DIEN_CC3DEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_CC4(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_CC4DEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_CC4(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_CC4DEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_CC4(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_CC4DEN) == (TMR_DIEN_CC4DEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_COM(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_COMDEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_COM(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_COMDEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_COM(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_COMDEN) == (TMR_DIEN_COMDEN)) ? 1UL : 0UL);
}

__STATIC_INLINE void DDL_TMR_EnableDMAReq_TRIG(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->DIEN, TMR_DIEN_TRGDEN);
}

__STATIC_INLINE void DDL_TMR_DisableDMAReq_TRIG(TMR_TypeDef *TMRx)
{
  CLEAR_BIT(TMRx->DIEN, TMR_DIEN_TRGDEN);
}

__STATIC_INLINE uint32_t DDL_TMR_IsEnabledDMAReq_TRIG(TMR_TypeDef *TMRx)
{
  return ((READ_BIT(TMRx->DIEN, TMR_DIEN_TRGDEN) == (TMR_DIEN_TRGDEN)) ? 1UL : 0UL);
}


__STATIC_INLINE void DDL_TMR_GenerateEvent_UPDATE(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_UEG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_CC1(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_CC1EG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_CC2(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_CC2EG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_CC3(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_CC3EG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_CC4(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_CC4EG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_COM(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_COMG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_TRIG(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_TEG);
}

__STATIC_INLINE void DDL_TMR_GenerateEvent_BRK(TMR_TypeDef *TMRx)
{
  SET_BIT(TMRx->CEG, TMR_CEG_BEG);
}

 
#if defined(USE_FULL_DDL_DRIVER)
 
ErrorStatus DDL_TMR_DeInit(TMR_TypeDef *TMRx);
void DDL_TMR_StructInit(DDL_TMR_InitTypeDef *TMR_InitStruct);
ErrorStatus DDL_TMR_Init(TMR_TypeDef *TMRx, DDL_TMR_InitTypeDef *TMR_InitStruct);
void DDL_TMR_OC_StructInit(DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct);
ErrorStatus DDL_TMR_OC_Init(TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_OC_InitTypeDef *TMR_OC_InitStruct);
void DDL_TMR_IC_StructInit(DDL_TMR_IC_InitTypeDef *TMR_ICInitStruct);
ErrorStatus DDL_TMR_IC_Init(TMR_TypeDef *TMRx, uint32_t Channel, DDL_TMR_IC_InitTypeDef *TMR_IC_InitStruct);
void DDL_TMR_ENCODER_StructInit(DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct);
ErrorStatus DDL_TMR_ENCODER_Init(TMR_TypeDef *TMRx, DDL_TMR_ENCODER_InitTypeDef *TMR_EncoderInitStruct);
void DDL_TMR_HALLSENSOR_StructInit(DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct);
ErrorStatus DDL_TMR_HALLSENSOR_Init(TMR_TypeDef *TMRx, DDL_TMR_HALLSENSOR_InitTypeDef *TMR_HallSensorInitStruct);
void DDL_TMR_BDT_StructInit(DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct);
ErrorStatus DDL_TMR_BDT_Init(TMR_TypeDef *TMRx, DDL_TMR_BDT_InitTypeDef *TMR_BDTInitStruct);
#endif /* USE_FULL_DDL_DRIVER */


 
#endif /* TMR1 || TMR2 || TMR3 || TMR4 */

 
#ifdef __cplusplus
}
#endif
 
#endif /* G32R4xx_DDL_TMR_H */