g32r4xx_ddl_usart.c

Go to the documentation of this file.

 
#if defined(USE_FULL_DDL_DRIVER)
 
/* Includes ------------------------------------------------------------------*/
#include "g32r4xx_ddl_usart.h"
#include "g32r4xx_ddl_rcm.h"
#ifdef  USE_FULL_ASSERT
#include "g32_assert.h"
#else
#define ASSERT_PARAM(_PARAM_) ((void)0U)
#endif

 
#if defined (USART1) || defined (USART2)

 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/

 
 
/* Private macros ------------------------------------------------------------*/
 
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
 *              divided by the smallest oversampling used on the USART (i.e. 8)    */
#define IS_DDL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
 
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_DDL_USART_BR_MIN(__VALUE__) ((__VALUE__) >= 16U)
 
#define IS_DDL_USART_DIRECTION(__VALUE__) (((__VALUE__) == DDL_USART_DIRECTION_NONE) \
                                          || ((__VALUE__) == DDL_USART_DIRECTION_RX) \
                                          || ((__VALUE__) == DDL_USART_DIRECTION_TX) \
                                          || ((__VALUE__) == DDL_USART_DIRECTION_TX_RX))
 
#define IS_DDL_USART_PARITY(__VALUE__) (((__VALUE__) == DDL_USART_PARITY_NONE) \
                                       || ((__VALUE__) == DDL_USART_PARITY_EVEN) \
                                       || ((__VALUE__) == DDL_USART_PARITY_ODD))
 
#define IS_DDL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == DDL_USART_DATAWIDTH_8B) \
                                          || ((__VALUE__) == DDL_USART_DATAWIDTH_9B))
 
#define IS_DDL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == DDL_USART_OVERSAMPLING_16) \
                                             || ((__VALUE__) == DDL_USART_OVERSAMPLING_8))
 
#define IS_DDL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == DDL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                                 || ((__VALUE__) == DDL_USART_LASTCLKPULSE_OUTPUT))
 
#define IS_DDL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == DDL_USART_PHASE_1EDGE) \
                                           || ((__VALUE__) == DDL_USART_PHASE_2EDGE))
 
#define IS_DDL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == DDL_USART_POLARITY_LOW) \
                                              || ((__VALUE__) == DDL_USART_POLARITY_HIGH))
 
#define IS_DDL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == DDL_USART_CLOCK_DISABLE) \
                                            || ((__VALUE__) == DDL_USART_CLOCK_ENABLE))
 
#define IS_DDL_USART_STOPBITS(__VALUE__) (((__VALUE__) == DDL_USART_STOPBITS_0_5) \
                                         || ((__VALUE__) == DDL_USART_STOPBITS_1) \
                                         || ((__VALUE__) == DDL_USART_STOPBITS_1_5) \
                                         || ((__VALUE__) == DDL_USART_STOPBITS_2))
 
#define IS_DDL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == DDL_USART_HWCONTROL_NONE) \
                                          || ((__VALUE__) == DDL_USART_HWCONTROL_RTS) \
                                          || ((__VALUE__) == DDL_USART_HWCONTROL_CTS) \
                                          || ((__VALUE__) == DDL_USART_HWCONTROL_RTS_CTS))

 
/* Private function prototypes -----------------------------------------------*/
 
/* Exported functions --------------------------------------------------------*/


ErrorStatus DDL_USART_DeInit(USART_TypeDef *USARTx)
{
  ErrorStatus status = SUCCESS;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_UART_INSTANCE(USARTx));
 
  DDL_RCM_Unlock();
 
  if (USARTx == USART1)
  {
    /* Force reset of USART clock */
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_USART1);
 
    /* Release reset of USART clock */
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_USART1);
  }
  else if (USARTx == USART2)
  {
    /* Force reset of USART clock */
    DDL_RCM_EnableAPBReset(DDL_RCM_APB_RESET_USART2);
 
    /* Release reset of USART clock */
    DDL_RCM_DisableAPBReset(DDL_RCM_APB_RESET_USART2);
  }
  else
  {
    status = ERROR;
  }
 
  return (status);
}

ErrorStatus DDL_USART_Init(USART_TypeDef *USARTx, DDL_USART_InitTypeDef *USART_InitStruct)
{
  ErrorStatus status = ERROR;
  uint32_t periphclk = DDL_RCM_PERIPH_FREQUENCY_NO;
  DDL_RCM_ClocksTypeDef rcc_clocks;
 
  /* Check the parameters */
  ASSERT_PARAM(IS_UART_INSTANCE(USARTx));
  ASSERT_PARAM(IS_DDL_USART_BAUDRATE(USART_InitStruct->BaudRate));
  ASSERT_PARAM(IS_DDL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
  ASSERT_PARAM(IS_DDL_USART_STOPBITS(USART_InitStruct->StopBits));
  ASSERT_PARAM(IS_DDL_USART_PARITY(USART_InitStruct->Parity));
  ASSERT_PARAM(IS_DDL_USART_DIRECTION(USART_InitStruct->TransferDirection));
  ASSERT_PARAM(IS_DDL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
  ASSERT_PARAM(IS_DDL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
 
  /* USART needs to be in disabled state, in order to be able to configure some bits in
     CTRLx registers */
  if (DDL_USART_IsEnabled(USARTx) == 0U)
  {
    /*---------------------------- USART CTRL1 Configuration -----------------------
     * Configure USARTx CTRL1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
     * - DataWidth:          USART_CTRL1_DBLCFG bits according to USART_InitStruct->DataWidth value
     * - Parity:             USART_CTRL1_PCEN, USART_CTRL1_PCFG bits according to USART_InitStruct->Parity value
     * - TransferDirection:  USART_CTRL1_TXEN, USART_CTRL1_RXEN bits according to USART_InitStruct->TransferDirection value
     * - Oversampling:       USART_CTRL1_OSMCFG bit according to USART_InitStruct->OverSampling value.
     */
    MODIFY_REG(USARTx->CTRL1,
               (USART_CTRL1_DBLCFG | USART_CTRL1_PCEN | USART_CTRL1_PCFG |
                USART_CTRL1_TXEN | USART_CTRL1_RXEN | USART_CTRL1_OSMCFG),
               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
 
    /*---------------------------- USART CTRL2 Configuration -----------------------
     * Configure USARTx CTRL2 (Stop bits) with parameters:
     * - Stop Bits:          USART_CTRL2_STOPCFG bits according to USART_InitStruct->StopBits value.
     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using DDL_USART_ClockInit().
     */
    DDL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
 
    /*---------------------------- USART CTRL3 Configuration -----------------------
     * Configure USARTx CTRL3 (Hardware Flow Control) with parameters:
     * - HardwareFlowControl: USART_CTRL3_RTSEN, USART_CTRL3_CTSEN bits according to USART_InitStruct->HardwareFlowControl value.
     */
    DDL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
 
    /*---------------------------- USART BRR Configuration -----------------------
     * Retrieve Clock frequency used for USART Peripheral
     */
    DDL_RCM_GetSystemClocksFreq(&rcc_clocks);
 
    periphclk = rcc_clocks.PCLK_Frequency;
 
    /* Configure the USART Baud Rate :
       - valid baud rate value (different from 0) is required
       - Peripheral clock as returned by RCM service, should be valid (different from 0).
    */
    if ((periphclk != DDL_RCM_PERIPH_FREQUENCY_NO)
        && (USART_InitStruct->BaudRate != 0U))
    {
      status = SUCCESS;
      DDL_USART_SetBaudRate(USARTx,
                           periphclk,
                           USART_InitStruct->OverSampling,
                           USART_InitStruct->BaudRate);
 
      /* Check BR is greater than or equal to 16d */
      ASSERT_PARAM(IS_DDL_USART_BR_MIN(USARTx->BR));
    }
  }
 
  return (status);
}

 
void DDL_USART_StructInit(DDL_USART_InitTypeDef *USART_InitStruct)
{
  /* Set USART_InitStruct fields to default values */
  USART_InitStruct->BaudRate            = 9600U;
  USART_InitStruct->DataWidth           = DDL_USART_DATAWIDTH_8B;
  USART_InitStruct->StopBits            = DDL_USART_STOPBITS_1;
  USART_InitStruct->Parity              = DDL_USART_PARITY_NONE ;
  USART_InitStruct->TransferDirection   = DDL_USART_DIRECTION_TX_RX;
  USART_InitStruct->HardwareFlowControl = DDL_USART_HWCONTROL_NONE;
  USART_InitStruct->OverSampling        = DDL_USART_OVERSAMPLING_16;
}

ErrorStatus DDL_USART_ClockInit(USART_TypeDef *USARTx, DDL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
  ErrorStatus status = SUCCESS;
 
  /* Check USART Instance and Clock signal output parameters */
  ASSERT_PARAM(IS_UART_INSTANCE(USARTx));
  ASSERT_PARAM(IS_DDL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
 
  /* USART needs to be in disabled state, in order to be able to configure some bits in
     CTRLx registers */
  if (DDL_USART_IsEnabled(USARTx) == 0U)
  {
    /*---------------------------- USART CTRL2 Configuration -----------------------*/
    /* If Clock signal has to be output */
    if (USART_ClockInitStruct->ClockOutput == DDL_USART_CLOCK_DISABLE)
    {
      /* Deactivate Clock signal delivery :
       * - Disable Clock Output:        USART_CTRL2_CLKEN cleared
       */
      DDL_USART_DisableSCLKOutput(USARTx);
    }
    else
    {
      /* Ensure USART instance is USART capable */
      ASSERT_PARAM(IS_USART_INSTANCE(USARTx));
 
      /* Check clock related parameters */
      ASSERT_PARAM(IS_DDL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
      ASSERT_PARAM(IS_DDL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
      ASSERT_PARAM(IS_DDL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
 
      /*---------------------------- USART CTRL2 Configuration -----------------------
       * Configure USARTx CTRL2 (Clock signal related bits) with parameters:
       * - Enable Clock Output:         USART_CTRL2_CLKEN set
       * - Clock Polarity:              USART_CTRL2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
       * - Clock Phase:                 USART_CTRL2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
       * - Last Bit Clock Pulse Output: USART_CTRL2_LBCPOEN bit according to USART_ClockInitStruct->LastBitClockPulse value.
       */
      MODIFY_REG(USARTx->CTRL2,
                 USART_CTRL2_CLKEN | USART_CTRL2_CPHA | USART_CTRL2_CPOL | USART_CTRL2_LBCPOEN,
                 USART_CTRL2_CLKEN | USART_ClockInitStruct->ClockPolarity |
                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
    }
  }
  /* Else (USART not in Disabled state => return ERROR */
  else
  {
    status = ERROR;
  }
 
  return (status);
}

void DDL_USART_ClockStructInit(DDL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
  /* Set DDL_USART_ClockInitStruct fields with default values */
  USART_ClockInitStruct->ClockOutput       = DDL_USART_CLOCK_DISABLE;
  USART_ClockInitStruct->ClockPolarity     = DDL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = DDL_USART_CLOCK_DISABLE */
  USART_ClockInitStruct->ClockPhase        = DDL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = DDL_USART_CLOCK_DISABLE */
  USART_ClockInitStruct->LastBitClockPulse = DDL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = DDL_USART_CLOCK_DISABLE */
}



 
#endif /* USART1 || USART2 */

 
#endif /* USE_FULL_DDL_DRIVER */