G32R430 Device Driver Layer v1.0.4
G32R4xx Device Driver Layer API Reference
ADC instance - Offset number

Macros

#define DDL_ADC16_OFFSET_0   ADC_OFFSET0_REGOFFSET
#define DDL_ADC16_OFFSET_1   ADC_OFFSET1_REGOFFSET
#define DDL_ADC16_OFFSET_2   ADC_OFFSET2_REGOFFSET
#define DDL_ADC16_OFFSET_3   ADC_OFFSET3_REGOFFSET
#define DDL_ADC16_OFFSET_4   ADC_OFFSET4_REGOFFSET
#define DDL_ADC16_OFFSET_5   ADC_OFFSET5_REGOFFSET

Detailed Description

Macro Definition Documentation

◆ DDL_ADC16_OFFSET_0

#define DDL_ADC16_OFFSET_0   ADC_OFFSET0_REGOFFSET

ADC offset number 0: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 576 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_OFFSET_1

#define DDL_ADC16_OFFSET_1   ADC_OFFSET1_REGOFFSET

ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 577 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_OFFSET_2

#define DDL_ADC16_OFFSET_2   ADC_OFFSET2_REGOFFSET

ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 578 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_OFFSET_3

#define DDL_ADC16_OFFSET_3   ADC_OFFSET3_REGOFFSET

ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 579 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_OFFSET_4

#define DDL_ADC16_OFFSET_4   ADC_OFFSET4_REGOFFSET

ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 580 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_OFFSET_5

#define DDL_ADC16_OFFSET_5   ADC_OFFSET5_REGOFFSET

ADC offset number 5: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)

Definition at line 581 of file g32r4xx_ddl_adc16.h.