ADC group regular - Sequencer discontinuous mode

Macros
#define	DDL_ADC16_REG_SEQ_DISCONT_DISABLE   (0x00000000UL)
#define	DDL_ADC16_REG_SEQ_DISCONT_1RANK   ( ADC_CFGR_DISCEN)
#define	DDL_ADC16_REG_SEQ_DISCONT_2RANKS   ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC16_REG_SEQ_DISCONT_3RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
#define	DDL_ADC16_REG_SEQ_DISCONT_4RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
#define	DDL_ADC16_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
#define	DDL_ADC16_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

Detailed Description

Macro Definition Documentation

DDL_ADC16_REG_SEQ_DISCONT_1RANK

#define DDL_ADC16_REG_SEQ_DISCONT_1RANK   ( ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 346 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_2RANKS

#define DDL_ADC16_REG_SEQ_DISCONT_2RANKS   ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 347 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_3RANKS

#define DDL_ADC16_REG_SEQ_DISCONT_3RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 348 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_4RANKS

#define DDL_ADC16_REG_SEQ_DISCONT_4RANKS   ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 349 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_5RANKS

#define DDL_ADC16_REG_SEQ_DISCONT_5RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 350 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_6RANKS

#define DDL_ADC16_REG_SEQ_DISCONT_6RANKS   (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 351 of file g32r4xx_ddl_adc16.h.

DDL_ADC16_REG_SEQ_DISCONT_DISABLE

#define DDL_ADC16_REG_SEQ_DISCONT_DISABLE   (0x00000000UL)

ADC group regular sequencer discontinuous mode disable

Definition at line 345 of file g32r4xx_ddl_adc16.h.