Macros
#define	DDL_ADC16_REG_SEQ_SCAN_DISABLE (0x00000000UL)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_RL_0)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_RL_1 )
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_RL_1 \| ADC_SQR1_RL_0)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_RL_2 )
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_RL_2 \| ADC_SQR1_RL_0)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_RL_2 \| ADC_SQR1_RL_1 )
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_RL_2 \| ADC_SQR1_RL_1 \| ADC_SQR1_RL_0)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_RL_3 )
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_RL_3 \| ADC_SQR1_RL_0)
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_RL_3 \| ADC_SQR1_RL_1 )
#define	DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_RL_3 \| ADC_SQR1_RL_1 \| ADC_SQR1_RL_0)

Detailed Description

Macro Definition Documentation

◆ DDL_ADC16_REG_SEQ_SCAN_DISABLE

#define DDL_ADC16_REG_SEQ_SCAN_DISABLE (0x00000000UL)

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 326 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_RL_3 | ADC_SQR1_RL_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 335 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 336 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_RL_3 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 337 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_RL_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 327 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_RL_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 328 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_RL_1 | ADC_SQR1_RL_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 329 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_RL_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 330 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_RL_2 | ADC_SQR1_RL_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 331 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 332 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_RL_2 | ADC_SQR1_RL_1 | ADC_SQR1_RL_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 333 of file g32r4xx_ddl_adc16.h.

◆ DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS

#define DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_RL_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 334 of file g32r4xx_ddl_adc16.h.

Macros