Topics
	ADC group regular - Trigger source
	ADC group regular - Trigger edge
	ADC group regular - Sequencer scan length
	ADC group regular - Sequencer discontinuous mode
	ADC group regular - Sequencer ranks
	ADC group injected - Sequencer scan length
	ADC group injected - Sequencer discontinuous mode
	Multimode - Mode
	ADC DISABLE COMMAND
	ADC instance - Single-ended channels
	ADC instance - Differential channels

Macros
#define	ADC_SQR1_REGOFFSET (0x00000000UL)
#define	ADC_SQR2_REGOFFSET (0x00000100UL)
#define	ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET)
#define	ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define	ADC_REG_RANK_ID_SQRX_MASK (0x1F)
#define	ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
#define	ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
#define	ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
#define	ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
#define	ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR1_SQ5_Pos)
#define	ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR1_SQ6_Pos)
#define	ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR1_SQ7_Pos)
#define	ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
#define	ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
#define	ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR2_SQ10_Pos)
#define	ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR2_SQ11_Pos)
#define	ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR2_SQ12_Pos)
#define	ADC_JDR1_REGOFFSET (0x00000000UL)
#define	ADC_JDR2_REGOFFSET (0x00000100UL)
#define	ADC_JDR3_REGOFFSET (0x00000200UL)
#define	ADC_JDR4_REGOFFSET (0x00000300UL)
#define	ADC_INJ_JDRX_REGOFFSET_MASK
#define	ADC_INJ_RANK_ID_JSQR_MASK (0x1F)
#define	ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
#define	ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define	ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define	ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define	ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define	ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */
#define	ADC_REG_TRIG_SOURCE_MASK
#define	ADC_REG_TRIG_EDGE_MASK
#define	ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
#define	ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
#define	ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */
#define	ADC_INJ_TRIG_SOURCE_MASK
#define	ADC_INJ_TRIG_EDGE_MASK
#define	ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
#define	ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
#define	ADC16_CFGR_AWD1CH (0x7UL << ADC_CFGR_AWD1CH_Pos)
#define	ADC_CHANNEL_ID_NUMBER_MASK (ADC16_CFGR_AWD1CH)
#define	ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
#define	ADC_CHANNEL_ID_MASK
#define	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
#define	ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define	ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define	ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
#define	ADC_SMPR1_REGOFFSET (0x00000000UL)
#define	ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET)
#define	ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define	ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define	ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
#define	ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define	ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
#define	ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
#define	ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define	ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define	ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define	ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define	ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define	ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define	ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET \| (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define	ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET \| (( 4UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define	ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET \| (( 8UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define	ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET \| ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define	ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET \| ((16UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define	ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET \| ((20UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define	ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define	ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define	ADC_AWD_CR3_REGOFFSET (0x00200000UL)
#define	ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define	ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000010UL)
#define	ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_CR1_CHANNEL_MASK (ADC16_CFGR_AWD1CH \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR23_CHANNEL_MASK)
#define	ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define	ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define	ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define	ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET \| ADC_AWD_TR2_REGOFFSET \| ADC_AWD_TR3_REGOFFSET)
#define	ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define	ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define	ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define	ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
#define	ADC_OFFSET0_REGOFFSET (0x00000000UL)
#define	ADC_OFFSET1_REGOFFSET (0x00000001UL)
#define	ADC_OFFSET2_REGOFFSET (0x00000002UL)
#define	ADC_OFFSET3_REGOFFSET (0x00000003UL)
#define	ADC_OFFSET4_REGOFFSET (0x00000004UL)
#define	ADC_OFFSET5_REGOFFSET (0x00000005UL)
#define	ADC_OFFSETx_REGOFFSET_MASK
#define	ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define	ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define	ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define	ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
#define	ADC_CR_BITS_PROPERTY_RS (ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Detailed Description

Macro Definition Documentation

◆ ADC16_CFGR_AWD1CH

#define ADC16_CFGR_AWD1CH (0x7UL << ADC_CFGR_AWD1CH_Pos)

Definition at line 185 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR12_REGOFFSETGAP_MASK

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 250 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR12_REGOFFSETGAP_VAL

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000010UL)

Definition at line 251 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR1_CHANNEL_MASK

#define ADC_AWD_CR1_CHANNEL_MASK (ADC16_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 255 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR1_REGOFFSET

#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)

Definition at line 244 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR23_CHANNEL_MASK

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 256 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR2_REGOFFSET

#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)

Definition at line 245 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR3_REGOFFSET

#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)

Definition at line 246 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CR_ALL_CHANNEL_MASK

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 257 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CRX_REGOFFSET_MASK

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 253 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_CRX_REGOFFSET_POS

#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 259 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TR1_REGOFFSET

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 262 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TR2_REGOFFSET

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 263 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TR3_REGOFFSET

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 264 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TRX_BIT_HIGH_MASK

#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */

Definition at line 267 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TRX_BIT_HIGH_POS

#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */

Definition at line 268 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TRX_BIT_HIGH_SHIFT4

#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */

Definition at line 269 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TRX_REGOFFSET_MASK

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 265 of file g32r4xx_ddl_adc16.h.

◆ ADC_AWD_TRX_REGOFFSET_POS

#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

Definition at line 266 of file g32r4xx_ddl_adc16.h.

◆ ADC_CFGR_AWD1EN_BITOFFSET_POS

#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)

Definition at line 285 of file g32r4xx_ddl_adc16.h.

◆ ADC_CFGR_AWD1SGL_BITOFFSET_POS

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)

Definition at line 284 of file g32r4xx_ddl_adc16.h.

◆ ADC_CFGR_JAWD1EN_BITOFFSET_POS

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)

Definition at line 286 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_0_BITFIELD

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 219 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_0_NUMBER

#define ADC_CHANNEL_0_NUMBER (0x00000000UL)

Definition at line 210 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_0_SMP

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

Definition at line 228 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_1_BITFIELD

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 220 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_1_NUMBER

#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)

Definition at line 211 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_1_SMP

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 4UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

Definition at line 229 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_2_BITFIELD

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 221 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_2_NUMBER

#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)

Definition at line 212 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_2_SMP

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 8UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

Definition at line 230 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_3_BITFIELD

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 222 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_3_NUMBER

#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 213 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_3_SMP

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

Definition at line 231 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_4_BITFIELD

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 223 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_4_NUMBER

#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)

Definition at line 214 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_4_SMP

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((16UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

Definition at line 232 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_5_BITFIELD

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 224 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_5_NUMBER

#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 215 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_5_SMP

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((20UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

Definition at line 233 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_BITFIELD_MASK

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 187 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_INTERNAL_CH

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */

Definition at line 195 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_INTERNAL_CH_2

#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 196 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_INTERNAL_CH_MASK

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 197 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_MASK

#define ADC_CHANNEL_ID_MASK

Value:

(ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \

| ADC_CHANNEL_ID_INTERNAL_CH_MASK)

ADC_CHANNEL_ID_BITFIELD_MASK

#define ADC_CHANNEL_ID_BITFIELD_MASK

Definition g32r4xx_ddl_adc16.h:187

ADC_CHANNEL_ID_INTERNAL_CH_MASK

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK

Definition g32r4xx_ddl_adc16.h:197

ADC_CHANNEL_ID_NUMBER_MASK

#define ADC_CHANNEL_ID_NUMBER_MASK

Definition g32r4xx_ddl_adc16.h:186

Definition at line 189 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)

Definition at line 188 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_NUMBER_MASK

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC16_CFGR_AWD1CH)

Definition at line 186 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ8) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

Definition at line 192 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_SMPRX_REGOFFSET_MASK

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET)

Definition at line 202 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_SMPx_BITOFFSET_MASK

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)

Definition at line 205 of file g32r4xx_ddl_adc16.h.

◆ ADC_CHANNEL_SMPx_BITOFFSET_POS

#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

Definition at line 206 of file g32r4xx_ddl_adc16.h.

◆ ADC_CR_BITS_PROPERTY_RS

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 290 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_JDRX_REGOFFSET_MASK

#define ADC_INJ_JDRX_REGOFFSET_MASK

Value:

(ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \

| ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

ADC_JDR4_REGOFFSET

#define ADC_JDR4_REGOFFSET

Definition g32r4xx_ddl_adc16.h:111

ADC_JDR1_REGOFFSET

#define ADC_JDR1_REGOFFSET

Definition g32r4xx_ddl_adc16.h:108

ADC_JDR2_REGOFFSET

#define ADC_JDR2_REGOFFSET

Definition g32r4xx_ddl_adc16.h:109

ADC_JDR3_REGOFFSET

#define ADC_JDR3_REGOFFSET

Definition g32r4xx_ddl_adc16.h:110

Definition at line 113 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_RANK_1_JSQR_BITOFFSET_POS

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)

Definition at line 120 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_RANK_2_JSQR_BITOFFSET_POS

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)

Definition at line 121 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_RANK_3_JSQR_BITOFFSET_POS

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)

Definition at line 122 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_RANK_4_JSQR_BITOFFSET_POS

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)

Definition at line 123 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_RANK_ID_JSQR_MASK

#define ADC_INJ_RANK_ID_JSQR_MASK (0x1F)

Definition at line 115 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_TRIG_EDGE_MASK

#define ADC_INJ_TRIG_EDGE_MASK

Value:

(((DDL_ADC16_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 168 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_TRIG_EXT_EDGE_DEFAULT

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge */

Definition at line 155 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_TRIG_EXTEN_BITOFFSET_POS

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)

Definition at line 175 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)

Definition at line 174 of file g32r4xx_ddl_adc16.h.

◆ ADC_INJ_TRIG_SOURCE_MASK

#define ADC_INJ_TRIG_SOURCE_MASK

Value:

(((DDL_ADC16_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

Definition at line 160 of file g32r4xx_ddl_adc16.h.

◆ ADC_JDR1_REGOFFSET

#define ADC_JDR1_REGOFFSET (0x00000000UL)

Definition at line 108 of file g32r4xx_ddl_adc16.h.

◆ ADC_JDR2_REGOFFSET

#define ADC_JDR2_REGOFFSET (0x00000100UL)

Definition at line 109 of file g32r4xx_ddl_adc16.h.

◆ ADC_JDR3_REGOFFSET

#define ADC_JDR3_REGOFFSET (0x00000200UL)

Definition at line 110 of file g32r4xx_ddl_adc16.h.

◆ ADC_JDR4_REGOFFSET

#define ADC_JDR4_REGOFFSET (0x00000300UL)

Definition at line 111 of file g32r4xx_ddl_adc16.h.

◆ ADC_JDRX_REGOFFSET_POS

#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

Definition at line 116 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET0_REGOFFSET

#define ADC_OFFSET0_REGOFFSET (0x00000000UL)

Definition at line 273 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET1_REGOFFSET

#define ADC_OFFSET1_REGOFFSET (0x00000001UL)

Definition at line 274 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET2_REGOFFSET

#define ADC_OFFSET2_REGOFFSET (0x00000002UL)

Definition at line 275 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET3_REGOFFSET

#define ADC_OFFSET3_REGOFFSET (0x00000003UL)

Definition at line 276 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET4_REGOFFSET

#define ADC_OFFSET4_REGOFFSET (0x00000004UL)

Definition at line 277 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSET5_REGOFFSET

#define ADC_OFFSET5_REGOFFSET (0x00000005UL)

Definition at line 278 of file g32r4xx_ddl_adc16.h.

◆ ADC_OFFSETx_REGOFFSET_MASK

#define ADC_OFFSETx_REGOFFSET_MASK

Value:

(ADC_OFFSET0_REGOFFSET | ADC_OFFSET1_REGOFFSET \
| ADC_OFFSET2_REGOFFSET | ADC_OFFSET3_REGOFFSET \
| ADC_OFFSET4_REGOFFSET | ADC_OFFSET5_REGOFFSET)

Definition at line 279 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_10_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR2_SQ10_Pos)

Definition at line 97 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_11_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR2_SQ11_Pos)

Definition at line 98 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_12_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR2_SQ12_Pos)

Definition at line 99 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_1_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)

Definition at line 88 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_2_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)

Definition at line 89 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_3_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)

Definition at line 90 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_4_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)

Definition at line 91 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_5_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR1_SQ5_Pos)

Definition at line 92 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_6_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR1_SQ6_Pos)

Definition at line 93 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_7_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR1_SQ7_Pos)

Definition at line 94 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_8_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)

Definition at line 95 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_9_SQRX_BITOFFSET_POS

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)

Definition at line 96 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_RANK_ID_SQRX_MASK

#define ADC_REG_RANK_ID_SQRX_MASK (0x1F)

Definition at line 84 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_SQRX_REGOFFSET_MASK

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET)

Definition at line 82 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_TRIG_EDGE_MASK

#define ADC_REG_TRIG_EDGE_MASK

Value:

(((DDL_ADC16_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

Definition at line 142 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_TRIG_EXT_EDGE_DEFAULT

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge */

Definition at line 129 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_TRIG_EXTEN_BITOFFSET_POS

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)

Definition at line 149 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_TRIG_EXTSEL_BITOFFSET_POS

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)

Definition at line 148 of file g32r4xx_ddl_adc16.h.

◆ ADC_REG_TRIG_SOURCE_MASK

#define ADC_REG_TRIG_SOURCE_MASK

Value:

(((DDL_ADC16_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
((ADC_CFGR_EXTSEL)                             << (4U * 1UL)) | \
((ADC_CFGR_EXTSEL)                             << (4U * 2UL)) | \
((ADC_CFGR_EXTSEL)                             << (4U * 3UL))  )

Definition at line 134 of file g32r4xx_ddl_adc16.h.

◆ ADC_SMPR1_REGOFFSET

#define ADC_SMPR1_REGOFFSET (0x00000000UL)

Definition at line 201 of file g32r4xx_ddl_adc16.h.

◆ ADC_SMPRX_REGOFFSET_POS

#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

Definition at line 203 of file g32r4xx_ddl_adc16.h.

◆ ADC_SQR1_REGOFFSET

#define ADC_SQR1_REGOFFSET (0x00000000UL)

Definition at line 79 of file g32r4xx_ddl_adc16.h.

◆ ADC_SQR2_REGOFFSET

#define ADC_SQR2_REGOFFSET (0x00000100UL)

Definition at line 80 of file g32r4xx_ddl_adc16.h.

◆ ADC_SQRX_REGOFFSET_POS

#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

Definition at line 83 of file g32r4xx_ddl_adc16.h.

◆ ADC_TR1_HT1_BITOFFSET_POS

#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)

Definition at line 287 of file g32r4xx_ddl_adc16.h.

Topics

Macros

Detailed Description

Macro Definition Documentation

◆ ADC16_CFGR_AWD1CH

◆ ADC_AWD_CR12_REGOFFSETGAP_MASK

◆ ADC_AWD_CR12_REGOFFSETGAP_VAL

◆ ADC_AWD_CR1_CHANNEL_MASK

◆ ADC_AWD_CR1_REGOFFSET

◆ ADC_AWD_CR23_CHANNEL_MASK

◆ ADC_AWD_CR2_REGOFFSET

◆ ADC_AWD_CR3_REGOFFSET

◆ ADC_AWD_CR_ALL_CHANNEL_MASK

◆ ADC_AWD_CRX_REGOFFSET_MASK

◆ ADC_AWD_CRX_REGOFFSET_POS

◆ ADC_AWD_TR1_REGOFFSET

◆ ADC_AWD_TR2_REGOFFSET

◆ ADC_AWD_TR3_REGOFFSET

◆ ADC_AWD_TRX_BIT_HIGH_MASK

◆ ADC_AWD_TRX_BIT_HIGH_POS

◆ ADC_AWD_TRX_BIT_HIGH_SHIFT4

◆ ADC_AWD_TRX_REGOFFSET_MASK

◆ ADC_AWD_TRX_REGOFFSET_POS

◆ ADC_CFGR_AWD1EN_BITOFFSET_POS

◆ ADC_CFGR_AWD1SGL_BITOFFSET_POS

◆ ADC_CFGR_JAWD1EN_BITOFFSET_POS

◆ ADC_CHANNEL_0_BITFIELD

◆ ADC_CHANNEL_0_NUMBER

◆ ADC_CHANNEL_0_SMP

◆ ADC_CHANNEL_1_BITFIELD

◆ ADC_CHANNEL_1_NUMBER

◆ ADC_CHANNEL_1_SMP

◆ ADC_CHANNEL_2_BITFIELD

◆ ADC_CHANNEL_2_NUMBER

◆ ADC_CHANNEL_2_SMP

◆ ADC_CHANNEL_3_BITFIELD

◆ ADC_CHANNEL_3_NUMBER

◆ ADC_CHANNEL_3_SMP

◆ ADC_CHANNEL_4_BITFIELD

◆ ADC_CHANNEL_4_NUMBER

◆ ADC_CHANNEL_4_SMP

◆ ADC_CHANNEL_5_BITFIELD

◆ ADC_CHANNEL_5_NUMBER

◆ ADC_CHANNEL_5_SMP

◆ ADC_CHANNEL_ID_BITFIELD_MASK

◆ ADC_CHANNEL_ID_INTERNAL_CH

◆ ADC_CHANNEL_ID_INTERNAL_CH_2

◆ ADC_CHANNEL_ID_INTERNAL_CH_MASK

◆ ADC_CHANNEL_ID_MASK

◆ ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

◆ ADC_CHANNEL_ID_NUMBER_MASK

◆ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0

◆ ADC_CHANNEL_SMPRX_REGOFFSET_MASK

◆ ADC_CHANNEL_SMPx_BITOFFSET_MASK

◆ ADC_CHANNEL_SMPx_BITOFFSET_POS

◆ ADC_CR_BITS_PROPERTY_RS

◆ ADC_INJ_JDRX_REGOFFSET_MASK

◆ ADC_INJ_RANK_1_JSQR_BITOFFSET_POS

◆ ADC_INJ_RANK_2_JSQR_BITOFFSET_POS

◆ ADC_INJ_RANK_3_JSQR_BITOFFSET_POS

◆ ADC_INJ_RANK_4_JSQR_BITOFFSET_POS

◆ ADC_INJ_RANK_ID_JSQR_MASK

◆ ADC_INJ_TRIG_EDGE_MASK

◆ ADC_INJ_TRIG_EXT_EDGE_DEFAULT

◆ ADC_INJ_TRIG_EXTEN_BITOFFSET_POS

◆ ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS

◆ ADC_INJ_TRIG_SOURCE_MASK

◆ ADC_JDR1_REGOFFSET

◆ ADC_JDR2_REGOFFSET

◆ ADC_JDR3_REGOFFSET

◆ ADC_JDR4_REGOFFSET

◆ ADC_JDRX_REGOFFSET_POS

◆ ADC_OFFSET0_REGOFFSET

◆ ADC_OFFSET1_REGOFFSET

◆ ADC_OFFSET2_REGOFFSET

◆ ADC_OFFSET3_REGOFFSET

◆ ADC_OFFSET4_REGOFFSET

◆ ADC_OFFSET5_REGOFFSET

◆ ADC_OFFSETx_REGOFFSET_MASK

◆ ADC_REG_RANK_10_SQRX_BITOFFSET_POS