ADC_LL_Private_Constants

Macros
#define	ADC12_CLOCK_RATIO_VS_CPU_HIGHEST   (3968UL)
#define	ADC12_TIMEOUT_DISABLE_CPU_CYCLES   (ADC12_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define	ADC12_TIMEOUT_STOP_CONVERSION_CPU_CYCLES   (ADC12_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define	IS_DDL_ADC12_REG_TRIG_SOURCE(__ADC12_INSTANCE__, __REG_TRIG_SOURCE__)
#define	IS_DDL_ADC12_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define	IS_DDL_ADC12_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define	IS_DDL_ADC12_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define	IS_DDL_ADC12_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define	IS_DDL_ADC12_INJ_TRIG_SOURCE(__ADC12_INSTANCE__, __INJ_TRIG_SOURCE__)
#define	IS_DDL_ADC12_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define	IS_DDL_ADC12_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define	IS_DDL_ADC12_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define	IS_DDL_ADC12_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define	IS_DDL_ADC12_CHANNEL(__CHANNEL__)
#define	ADC_CLOCK_RATIO_VS_CPU_HIGHEST   (3968UL)
#define	ADC_TIMEOUT_DISABLE_CPU_CYCLES   (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define	ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES   (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define	IS_DDL_ADC16_LOW_POWER(__LOW_POWER__)
#define	IS_DDL_ADC16_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)
#define	IS_DDL_ADC16_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define	IS_DDL_ADC16_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define	IS_DDL_ADC16_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define	IS_DDL_ADC16_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define	IS_DDL_ADC16_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)
#define	IS_DDL_ADC16_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)
#define	IS_DDL_ADC16_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)
#define	IS_DDL_ADC16_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define	IS_DDL_ADC16_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define	IS_DDL_ADC16_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define	IS_DDL_ADC16_SINGLE_DIFFERENTIAL(__SINGLE_DIFFERENTIAL__)
#define	IS_DDL_ADC16_CHANNEL(__CHANNEL__)

Detailed Description

Macro Definition Documentation

ADC12_CLOCK_RATIO_VS_CPU_HIGHEST

#define ADC12_CLOCK_RATIO_VS_CPU_HIGHEST   (3968UL)

Definition at line 99 of file g32r4xx_ddl_adc12.c.

ADC12_TIMEOUT_DISABLE_CPU_CYCLES

#define ADC12_TIMEOUT_DISABLE_CPU_CYCLES   (ADC12_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 100 of file g32r4xx_ddl_adc12.c.

ADC12_TIMEOUT_STOP_CONVERSION_CPU_CYCLES

#define ADC12_TIMEOUT_STOP_CONVERSION_CPU_CYCLES   (ADC12_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 101 of file g32r4xx_ddl_adc12.c.

ADC_CLOCK_RATIO_VS_CPU_HIGHEST

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST   (3968UL)

Definition at line 101 of file g32r4xx_ddl_adc16.c.

ADC_TIMEOUT_DISABLE_CPU_CYCLES

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES   (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 102 of file g32r4xx_ddl_adc16.c.

ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES   (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)

Definition at line 103 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC12_CHANNEL

#define IS_DDL_ADC12_CHANNEL

(

__CHANNEL__

)

Value:

(((__CHANNEL__) == DDL_ADC12_CHANNEL_0)              \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_1)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_2)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_3)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_4)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_5)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_6)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_7)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_8)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_9)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_10)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_11)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_12)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_13)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_14)             \
|| ((__CHANNEL__) == DDL_ADC12_CHANNEL_15)             \
)

Definition at line 186 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_INJ_SEQ_SCAN_DISCONT_MODE

#define IS_DDL_ADC12_INJ_SEQ_SCAN_DISCONT_MODE

(

__INJ_SEQ_DISCONT_MODE__

)

Value:

(((__INJ_SEQ_DISCONT_MODE__) == DDL_ADC12_INJ_SEQ_DISCONT_DISABLE)              \
 || ((__INJ_SEQ_DISCONT_MODE__) == DDL_ADC12_INJ_SEQ_DISCONT_1RANK)             \
)

Definition at line 181 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_INJ_SEQ_SCAN_LENGTH

#define IS_DDL_ADC12_INJ_SEQ_SCAN_LENGTH

(

__INJ_SEQ_SCAN_LENGTH__

)

Value:

(((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC12_INJ_SEQ_SCAN_DISABLE)                  \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC12_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC12_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC12_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
)

Definition at line 174 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_INJ_TRIG_AUTO

#define IS_DDL_ADC12_INJ_TRIG_AUTO

(

__INJ_TRIG_AUTO__

)

Value:

(((__INJ_TRIG_AUTO__) == DDL_ADC12_INJ_TRIG_INDEPENDENT)                        \
 || ((__INJ_TRIG_AUTO__) == DDL_ADC12_INJ_TRIG_FROM_GRP_REGULAR)                \
)

Definition at line 169 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_INJ_TRIG_EXT_EDGE

#define IS_DDL_ADC12_INJ_TRIG_EXT_EDGE

(

__INJ_TRIG_EXT_EDGE__

)

Value:

(((__INJ_TRIG_EXT_EDGE__) == DDL_ADC12_INJ_TRIG_EXT_RISING)                     \
 || ((__INJ_TRIG_EXT_EDGE__) == DDL_ADC12_INJ_TRIG_EXT_DISABLE)                 \
)

Definition at line 164 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_INJ_TRIG_SOURCE

#define IS_DDL_ADC12_INJ_TRIG_SOURCE	(		__ADC12_INSTANCE__,
			__INJ_TRIG_SOURCE__ )

Value:

(((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_SOFTWARE)                         \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR1_TRGO)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR1_CC4)                \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR2_TRGO)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR2_CC1)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR3_CC4)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_TMR4_TRGO)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC12_INJ_TRIG_EXT_EINT_LINE15)                  \
)

Definition at line 153 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_REG_CONTINUOUS_MODE

#define IS_DDL_ADC12_REG_CONTINUOUS_MODE

(

__REG_CONTINUOUS_MODE__

)

Value:

(((__REG_CONTINUOUS_MODE__) == DDL_ADC12_REG_CONV_SINGLE)                       \
 || ((__REG_CONTINUOUS_MODE__) == DDL_ADC12_REG_CONV_CONTINUOUS)                \
)

Definition at line 143 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_REG_DMA_TRANSFER

#define IS_DDL_ADC12_REG_DMA_TRANSFER

(

__REG_DMA_TRANSFER__

)

Value:

(((__REG_DMA_TRANSFER__) == DDL_ADC12_REG_DMA_TRANSFER_DISABLE)                    \
 || ((__REG_DMA_TRANSFER__) == DDL_ADC12_REG_DMA_TRANSFER_ENABLE)              \
)

Definition at line 148 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_REG_SEQ_SCAN_DISCONT_MODE

#define IS_DDL_ADC12_REG_SEQ_SCAN_DISCONT_MODE

(

__REG_SEQ_DISCONT_MODE__

)

Value:

(((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_DISABLE)              \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_1RANK)             \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_2RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_3RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_4RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_5RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_6RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_7RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC12_REG_SEQ_DISCONT_8RANKS)            \
)

Definition at line 131 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_REG_SEQ_SCAN_LENGTH

#define IS_DDL_ADC12_REG_SEQ_SCAN_LENGTH

(

__REG_SEQ_SCAN_LENGTH__

)

Value:

(((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_DISABLE)                  \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_2RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_3RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_4RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_5RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_6RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_7RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_8RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_9RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_10RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_11RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_12RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_13RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC12_REG_SEQ_SCAN_ENABLE_14RANKS)        \
)

Definition at line 114 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC12_REG_TRIG_SOURCE

#define IS_DDL_ADC12_REG_TRIG_SOURCE	(		__ADC12_INSTANCE__,
			__REG_TRIG_SOURCE__ )

Value:

(((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_SOFTWARE)                         \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR1_CC1)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR1_CC2)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR1_CC3)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR2_CC2)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR3_TRGO)                 \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_TMR4_CC4)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC12_REG_TRIG_EXT_EINT_LINE11)               \
 )

Definition at line 103 of file g32r4xx_ddl_adc12.c.

IS_DDL_ADC16_CHANNEL

#define IS_DDL_ADC16_CHANNEL

(

__CHANNEL__

)

Value:

(((__CHANNEL__) == DDL_ADC16_CHANNEL_0)              \
|| ((__CHANNEL__) == DDL_ADC16_CHANNEL_1)             \
|| ((__CHANNEL__) == DDL_ADC16_CHANNEL_2)             \
|| ((__CHANNEL__) == DDL_ADC16_CHANNEL_3)             \
|| ((__CHANNEL__) == DDL_ADC16_CHANNEL_4)             \
|| ((__CHANNEL__) == DDL_ADC16_CHANNEL_5)             \
)

Definition at line 210 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_INJ_SEQ_SCAN_DISCONT_MODE

#define IS_DDL_ADC16_INJ_SEQ_SCAN_DISCONT_MODE

(

__INJ_SEQ_DISCONT_MODE__

)

Value:

(((__INJ_SEQ_DISCONT_MODE__) == DDL_ADC16_INJ_SEQ_DISCONT_DISABLE)              \
 || ((__INJ_SEQ_DISCONT_MODE__) == DDL_ADC16_INJ_SEQ_DISCONT_1RANK)             \
)

Definition at line 200 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_INJ_SEQ_SCAN_LENGTH

#define IS_DDL_ADC16_INJ_SEQ_SCAN_LENGTH

(

__INJ_SEQ_SCAN_LENGTH__

)

Value:

(((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC16_INJ_SEQ_SCAN_DISABLE)                  \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC16_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC16_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
 || ((__INJ_SEQ_SCAN_LENGTH__) == DDL_ADC16_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
)

Definition at line 193 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_INJ_TRIG_AUTO

#define IS_DDL_ADC16_INJ_TRIG_AUTO

(

__INJ_TRIG_AUTO__

)

Value:

(((__INJ_TRIG_AUTO__) == DDL_ADC16_INJ_TRIG_INDEPENDENT)                        \
 || ((__INJ_TRIG_AUTO__) == DDL_ADC16_INJ_TRIG_FROM_GRP_REGULAR)                \
)

Definition at line 188 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_INJ_TRIG_EXT_EDGE

#define IS_DDL_ADC16_INJ_TRIG_EXT_EDGE

(

__INJ_TRIG_EXT_EDGE__

)

Value:

(((__INJ_TRIG_EXT_EDGE__) == DDL_ADC16_INJ_TRIG_EXT_RISING)                     \
 || ((__INJ_TRIG_EXT_EDGE__) == DDL_ADC16_INJ_TRIG_EXT_FALLING)                 \
 || ((__INJ_TRIG_EXT_EDGE__) == DDL_ADC16_INJ_TRIG_EXT_RISINGFALLING)           \
)

Definition at line 182 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_INJ_TRIG_SOURCE

#define IS_DDL_ADC16_INJ_TRIG_SOURCE	(		__ADC_INSTANCE__,
			__INJ_TRIG_SOURCE__ )

Value:

(((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_SOFTWARE)                         \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR1_TRGO)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR1_CC4)                \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR2_TRGO)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR2_CC1)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR2_CC4)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR4_TRGO)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_EINT_LINE15)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR3_CC3)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR3_TRGO)                  \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_TMR3_CC1)                 \
 || ((__INJ_TRIG_SOURCE__) == DDL_ADC16_INJ_TRIG_EXT_LPTMROUT)                 \
)

Definition at line 167 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_LOW_POWER

#define IS_DDL_ADC16_LOW_POWER

(

__LOW_POWER__

)

Value:

(((__LOW_POWER__) == DDL_ADC16_LP_MODE_NONE)                                    \
 || ((__LOW_POWER__) == DDL_ADC16_LP_AUTOWAIT)                                  \
)

Definition at line 105 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_CONTINUOUS_MODE

#define IS_DDL_ADC16_REG_CONTINUOUS_MODE

(

__REG_CONTINUOUS_MODE__

)

Value:

(((__REG_CONTINUOUS_MODE__) == DDL_ADC16_REG_CONV_SINGLE)                       \
 || ((__REG_CONTINUOUS_MODE__) == DDL_ADC16_REG_CONV_CONTINUOUS)                \
)

Definition at line 151 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_DMA_TRANSFER

#define IS_DDL_ADC16_REG_DMA_TRANSFER

(

__REG_DMA_TRANSFER__

)

Value:

(((__REG_DMA_TRANSFER__) == DDL_ADC16_REG_DMA_TRANSFER_NONE)                    \
 || ((__REG_DMA_TRANSFER__) == DDL_ADC16_REG_DMA_TRANSFER_LIMITED)              \
 || ((__REG_DMA_TRANSFER__) == DDL_ADC16_REG_DMA_TRANSFER_UNLIMITED)            \
)

Definition at line 156 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_OVR_DATA_BEHAVIOR

#define IS_DDL_ADC16_REG_OVR_DATA_BEHAVIOR

(

__REG_OVR_DATA_BEHAVIOR__

)

Value:

(((__REG_OVR_DATA_BEHAVIOR__) == DDL_ADC16_REG_OVR_DATA_PRESERVED)              \
 || ((__REG_OVR_DATA_BEHAVIOR__) == DDL_ADC16_REG_OVR_DATA_OVERWRITTEN)         \
)

Definition at line 162 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_SEQ_SCAN_DISCONT_MODE

#define IS_DDL_ADC16_REG_SEQ_SCAN_DISCONT_MODE

(

__REG_SEQ_DISCONT_MODE__

)

Value:

(((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_DISABLE)              \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_1RANK)             \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_2RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_3RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_4RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_5RANKS)            \
 || ((__REG_SEQ_DISCONT_MODE__) == DDL_ADC16_REG_SEQ_DISCONT_6RANKS)            \
)

Definition at line 141 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_SEQ_SCAN_LENGTH

#define IS_DDL_ADC16_REG_SEQ_SCAN_LENGTH

(

__REG_SEQ_SCAN_LENGTH__

)

Value:

(((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_DISABLE)                  \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_2RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_3RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_4RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_5RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_6RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_7RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_8RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_9RANKS)         \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_10RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_11RANKS)        \
 || ((__REG_SEQ_SCAN_LENGTH__) == DDL_ADC16_REG_SEQ_SCAN_ENABLE_12RANKS)        \
)

Definition at line 126 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_REG_TRIG_SOURCE

#define IS_DDL_ADC16_REG_TRIG_SOURCE	(		__ADC_INSTANCE__,
			__REG_TRIG_SOURCE__ )

Value:

(((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_SOFTWARE)                         \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR1_CC1)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR1_CC2)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR1_CC3)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR2_CC2)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR3_TRGO)                 \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR4_CC4)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_EINT_LINE11)               \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR1_TRGO)                 \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR2_TRGO)                 \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR4_TRGO)                 \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_TMR3_CC4)                  \
 || ((__REG_TRIG_SOURCE__) == DDL_ADC16_REG_TRIG_EXT_LPTMROUT)                  \
 )

Definition at line 110 of file g32r4xx_ddl_adc16.c.

IS_DDL_ADC16_SINGLE_DIFFERENTIAL

#define IS_DDL_ADC16_SINGLE_DIFFERENTIAL

(

__SINGLE_DIFFERENTIAL__

)

Value:

(((__SINGLE_DIFFERENTIAL__) == DDL_ADC16_SINGLE_ENDED)              \
 || ((__SINGLE_DIFFERENTIAL__) == DDL_ADC16_DIFFERENTIAL_ENDED)             \
)

Definition at line 205 of file g32r4xx_ddl_adc16.c.