CHANNEL

Macros
#define	DDL_DMA_CHANNEL_0   0x00000000U /* Select Channel0 of DMA Instance */
#define	DDL_DMA_CHANNEL_1   DMA_SCFG_CHSEL_0 /* Select Channel1 of DMA Instance */
#define	DDL_DMA_CHANNEL_2   DMA_SCFG_CHSEL_1 /* Select Channel2 of DMA Instance */
#define	DDL_DMA_CHANNEL_3   (DMA_SCFG_CHSEL_0 | DMA_SCFG_CHSEL_1) /* Select Channel3 of DMA Instance */
#define	DDL_DMA_CHANNEL_4   DMA_SCFG_CHSEL_2 /* Select Channel4 of DMA Instance */
#define	DDL_DMA_CHANNEL_5   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0) /* Select Channel5 of DMA Instance */
#define	DDL_DMA_CHANNEL_6   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1) /* Select Channel6 of DMA Instance */
#define	DDL_DMA_CHANNEL_7   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel7 of DMA Instance */
#define	DDL_DMA_CHANNEL_8   DMA_SCFG_CHSEL_3 /* Select Channel8 of DMA Instance */
#define	DDL_DMA_CHANNEL_9   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_0) /* Select Channel9 of DMA Instance */
#define	DDL_DMA_CHANNEL_10   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1) /* Select Channel10 of DMA Instance */
#define	DDL_DMA_CHANNEL_11   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel11 of DMA Instance */
#define	DDL_DMA_CHANNEL_12   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2) /* Select Channel12 of DMA Instance */
#define	DDL_DMA_CHANNEL_13   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0) /* Select Channel13 of DMA Instance */
#define	DDL_DMA_CHANNEL_14   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1) /* Select Channel14 of DMA Instance */
#define	DDL_DMA_CHANNEL_15   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel15 of DMA Instance */

Detailed Description

Macro Definition Documentation

DDL_DMA_CHANNEL_0

#define DDL_DMA_CHANNEL_0   0x00000000U /* Select Channel0 of DMA Instance */

Definition at line 303 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_1

#define DDL_DMA_CHANNEL_1   DMA_SCFG_CHSEL_0 /* Select Channel1 of DMA Instance */

Definition at line 304 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_10

#define DDL_DMA_CHANNEL_10   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1) /* Select Channel10 of DMA Instance */

Definition at line 314 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_11

#define DDL_DMA_CHANNEL_11   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel11 of DMA Instance */

Definition at line 315 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_12

#define DDL_DMA_CHANNEL_12   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2) /* Select Channel12 of DMA Instance */

Definition at line 316 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_13

#define DDL_DMA_CHANNEL_13   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0) /* Select Channel13 of DMA Instance */

Definition at line 317 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_14

#define DDL_DMA_CHANNEL_14   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1) /* Select Channel14 of DMA Instance */

Definition at line 318 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_15

#define DDL_DMA_CHANNEL_15   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel15 of DMA Instance */

Definition at line 319 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_2

#define DDL_DMA_CHANNEL_2   DMA_SCFG_CHSEL_1 /* Select Channel2 of DMA Instance */

Definition at line 305 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_3

#define DDL_DMA_CHANNEL_3   (DMA_SCFG_CHSEL_0 | DMA_SCFG_CHSEL_1) /* Select Channel3 of DMA Instance */

Definition at line 306 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_4

#define DDL_DMA_CHANNEL_4   DMA_SCFG_CHSEL_2 /* Select Channel4 of DMA Instance */

Definition at line 307 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_5

#define DDL_DMA_CHANNEL_5   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_0) /* Select Channel5 of DMA Instance */

Definition at line 308 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_6

#define DDL_DMA_CHANNEL_6   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1) /* Select Channel6 of DMA Instance */

Definition at line 309 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_7

#define DDL_DMA_CHANNEL_7   (DMA_SCFG_CHSEL_2 | DMA_SCFG_CHSEL_1 | DMA_SCFG_CHSEL_0) /* Select Channel7 of DMA Instance */

Definition at line 310 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_8

#define DDL_DMA_CHANNEL_8   DMA_SCFG_CHSEL_3 /* Select Channel8 of DMA Instance */

Definition at line 312 of file g32r4xx_ddl_dma.h.

DDL_DMA_CHANNEL_9

#define DDL_DMA_CHANNEL_9   (DMA_SCFG_CHSEL_3 | DMA_SCFG_CHSEL_0) /* Select Channel9 of DMA Instance */

Definition at line 313 of file g32r4xx_ddl_dma.h.