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G32R430 Device Driver Layer v1.0.4
G32R4xx Device Driver Layer API Reference
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Macros | |
| #define | __DDL_RCM_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLP__, __PLLMUL__) |
| Helper macro to calculate the PLLCLK frequency on system domain. | |
| #define | __DDL_RCM_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) |
| Helper macro to calculate the HCLK frequency. | |
| #define | __DDL_RCM_CALC_PCLK_FREQ(__HCLKFREQ__, __APBPRESCALER__) |
| Helper macro to calculate the PCLK frequency (ABP). | |
| #define | __DDL_RCM_KEY 0x87E4 |
| #define | IS_DDL_RCM_LSE_DRIVE(__VALUE__) |
| #define __DDL_RCM_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__, | |
| __AHBPRESCALER__ ) |
Helper macro to calculate the HCLK frequency.
| __SYSCLKFREQ__ | SYSCLK frequency (based on HSE/HSI/PLLCLK) |
| __AHBPRESCALER__ | This parameter can be one of the following values: |
| HCLK | clock frequency (in Hz) |
Definition at line 470 of file g32r4xx_ddl_rcm.h.
| #define __DDL_RCM_CALC_PCLK_FREQ | ( | __HCLKFREQ__, | |
| __APBPRESCALER__ ) |
Helper macro to calculate the PCLK frequency (ABP).
| __HCLKFREQ__ | HCLK frequency |
| __APBPRESCALER__ | This parameter can be one of the following values: |
| PCLK1 | clock frequency (in Hz) |
Definition at line 483 of file g32r4xx_ddl_rcm.h.
| #define __DDL_RCM_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__, | |
| __PLLP__, | |||
| __PLLMUL__ ) |
Helper macro to calculate the PLLCLK frequency on system domain.
| __INPUTFREQ__ | PLL Input frequency (based on HSE/HSI) |
| __PLLP__ | This parameter can be between 0x1 to 0xF |
| __PLLMUL__ | This parameter can be between 0x0 to 0x3F |
| PLL | clock frequency (in Hz) |
Definition at line 453 of file g32r4xx_ddl_rcm.h.
| #define __DDL_RCM_KEY 0x87E4 |
Definition at line 485 of file g32r4xx_ddl_rcm.h.
| #define IS_DDL_RCM_LSE_DRIVE | ( | __VALUE__ | ) |
Definition at line 487 of file g32r4xx_ddl_rcm.h.