G32R430 Device Driver Layer v1.0.4
G32R4xx Device Driver Layer API Reference

Macros

#define DDL_TMR_CLOCKSOURCE_INTERNAL   0x00000000U
#define DDL_TMR_CLOCKSOURCE_EXT_MODE1   TMR_SMCTRL_SMFSEL
#define DDL_TMR_CLOCKSOURCE_EXT_MODE2   TMR_SMCTRL_ECEN

Detailed Description

Macro Definition Documentation

◆ DDL_TMR_CLOCKSOURCE_EXT_MODE1

#define DDL_TMR_CLOCKSOURCE_EXT_MODE1   TMR_SMCTRL_SMFSEL

Counter counts at each rising or falling edge on a selected input

Definition at line 746 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_CLOCKSOURCE_EXT_MODE2

#define DDL_TMR_CLOCKSOURCE_EXT_MODE2   TMR_SMCTRL_ECEN

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 747 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_CLOCKSOURCE_INTERNAL

#define DDL_TMR_CLOCKSOURCE_INTERNAL   0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 745 of file g32r4xx_ddl_tmr.h.