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#define	DDL_TMR_DMABURST_BASEADDR_CTRL1 (0x00000000U)
#define	DDL_TMR_DMABURST_BASEADDR_CTRL2 (TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_SMCTRL (TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_DIEN (TMR_DCTRL_DBADDR_1 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_STS (TMR_DCTRL_DBADDR_2)
#define	DDL_TMR_DMABURST_BASEADDR_CEG (TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CCM1 (TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_CCM2 (TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_1 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CCEN (TMR_DCTRL_DBADDR_3)
#define	DDL_TMR_DMABURST_BASEADDR_CNT (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_PSC (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_AUTORLD (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_1 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_REPCNT (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_2)
#define	DDL_TMR_DMABURST_BASEADDR_CC1 (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CC2 (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_1)
#define	DDL_TMR_DMABURST_BASEADDR_CC3 (TMR_DCTRL_DBADDR_3 \| TMR_DCTRL_DBADDR_2 \| TMR_DCTRL_DBADDR_1 \| TMR_DCTRL_DBADDR_0)
#define	DDL_TMR_DMABURST_BASEADDR_CC4 (TMR_DCTRL_DBADDR_4)
#define	DDL_TMR_DMABURST_BASEADDR_BDT (TMR_DCTRL_DBADDR_4 \| TMR_DCTRL_DBADDR_0)

Detailed Description

Macro Definition Documentation

◆ DDL_TMR_DMABURST_BASEADDR_AUTORLD

#define DDL_TMR_DMABURST_BASEADDR_AUTORLD (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)

TMRx_AUTORLD register is the DMA base address for DMA burst

Definition at line 887 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_BDT

#define DDL_TMR_DMABURST_BASEADDR_BDT (TMR_DCTRL_DBADDR_4 | TMR_DCTRL_DBADDR_0)

TMRx_BDT register is the DMA base address for DMA burst

Definition at line 893 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CC1

#define DDL_TMR_DMABURST_BASEADDR_CC1 (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)

TMRx_CC1 register is the DMA base address for DMA burst

Definition at line 889 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CC2

#define DDL_TMR_DMABURST_BASEADDR_CC2 (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)

TMRx_CC2 register is the DMA base address for DMA burst

Definition at line 890 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CC3

#define DDL_TMR_DMABURST_BASEADDR_CC3 (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)

TMRx_CC3 register is the DMA base address for DMA burst

Definition at line 891 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CC4

#define DDL_TMR_DMABURST_BASEADDR_CC4 (TMR_DCTRL_DBADDR_4)

TMRx_CC4 register is the DMA base address for DMA burst

Definition at line 892 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CCEN

#define DDL_TMR_DMABURST_BASEADDR_CCEN (TMR_DCTRL_DBADDR_3)

TMRx_CCEN register is the DMA base address for DMA burst

Definition at line 884 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CCM1

#define DDL_TMR_DMABURST_BASEADDR_CCM1 (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1)

TMRx_CCM1 register is the DMA base address for DMA burst

Definition at line 882 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CCM2

#define DDL_TMR_DMABURST_BASEADDR_CCM2 (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)

TMRx_CCM2 register is the DMA base address for DMA burst

Definition at line 883 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CEG

#define DDL_TMR_DMABURST_BASEADDR_CEG (TMR_DCTRL_DBADDR_2 | TMR_DCTRL_DBADDR_0)

TMRx_CEG register is the DMA base address for DMA burst

Definition at line 881 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CNT

#define DDL_TMR_DMABURST_BASEADDR_CNT (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_0)

TMRx_CNT register is the DMA base address for DMA burst

Definition at line 885 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CTRL1

#define DDL_TMR_DMABURST_BASEADDR_CTRL1 (0x00000000U)

TMRx_CTRL1 register is the DMA base address for DMA burst

Definition at line 876 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_CTRL2

#define DDL_TMR_DMABURST_BASEADDR_CTRL2 (TMR_DCTRL_DBADDR_0)

TMRx_CTRL2 register is the DMA base address for DMA burst

Definition at line 877 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_DIEN

#define DDL_TMR_DMABURST_BASEADDR_DIEN (TMR_DCTRL_DBADDR_1 | TMR_DCTRL_DBADDR_0)

TMRx_DIEN register is the DMA base address for DMA burst

Definition at line 879 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_PSC

#define DDL_TMR_DMABURST_BASEADDR_PSC (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_1)

TMRx_PSC register is the DMA base address for DMA burst

Definition at line 886 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_REPCNT

#define DDL_TMR_DMABURST_BASEADDR_REPCNT (TMR_DCTRL_DBADDR_3 | TMR_DCTRL_DBADDR_2)

TMRx_REPCNT register is the DMA base address for DMA burst

Definition at line 888 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_SMCTRL

#define DDL_TMR_DMABURST_BASEADDR_SMCTRL (TMR_DCTRL_DBADDR_1)

TMRx_SMCTRL register is the DMA base address for DMA burst

Definition at line 878 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_BASEADDR_STS

#define DDL_TMR_DMABURST_BASEADDR_STS (TMR_DCTRL_DBADDR_2)

TMRx_STS register is the DMA base address for DMA burst

Definition at line 880 of file g32r4xx_ddl_tmr.h.

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