Macros
#define	DDL_TMR_DMABURST_LENGTH_1TRANSFER (0x00000000U)
#define	DDL_TMR_DMABURST_LENGTH_2TRANSFERS (TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_3TRANSFERS (TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_4TRANSFERS (TMR_DCTRL_DBLEN_1 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_5TRANSFERS (TMR_DCTRL_DBLEN_2)
#define	DDL_TMR_DMABURST_LENGTH_6TRANSFERS (TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_7TRANSFERS (TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_8TRANSFERS (TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_1 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_9TRANSFERS (TMR_DCTRL_DBLEN_3)
#define	DDL_TMR_DMABURST_LENGTH_10TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_11TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_12TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_1 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_13TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_2)
#define	DDL_TMR_DMABURST_LENGTH_14TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_15TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_1)
#define	DDL_TMR_DMABURST_LENGTH_16TRANSFERS (TMR_DCTRL_DBLEN_3 \| TMR_DCTRL_DBLEN_2 \| TMR_DCTRL_DBLEN_1 \| TMR_DCTRL_DBLEN_0)
#define	DDL_TMR_DMABURST_LENGTH_17TRANSFERS (TMR_DCTRL_DBLEN_4)
#define	DDL_TMR_DMABURST_LENGTH_18TRANSFERS (TMR_DCTRL_DBLEN_4 \| TMR_DCTRL_DBLEN_0)

Detailed Description

Macro Definition Documentation

◆ DDL_TMR_DMABURST_LENGTH_10TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_10TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 910 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_11TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_11TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 911 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_12TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_12TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 912 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_13TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_13TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 913 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_14TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_14TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 914 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_15TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_15TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 915 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_16TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_16TRANSFERS (TMR_DCTRL_DBLEN_3 | TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 916 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_17TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_17TRANSFERS (TMR_DCTRL_DBLEN_4)

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 917 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_18TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_18TRANSFERS (TMR_DCTRL_DBLEN_4 | TMR_DCTRL_DBLEN_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 918 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_1TRANSFER

#define DDL_TMR_DMABURST_LENGTH_1TRANSFER (0x00000000U)

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 901 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_2TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_2TRANSFERS (TMR_DCTRL_DBLEN_0)

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 902 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_3TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_3TRANSFERS (TMR_DCTRL_DBLEN_1)

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 903 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_4TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_4TRANSFERS (TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 904 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_5TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_5TRANSFERS (TMR_DCTRL_DBLEN_2)

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 905 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_6TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_6TRANSFERS (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 906 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_7TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_7TRANSFERS (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 907 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_8TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_8TRANSFERS (TMR_DCTRL_DBLEN_2 | TMR_DCTRL_DBLEN_1 | TMR_DCTRL_DBLEN_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 908 of file g32r4xx_ddl_tmr.h.

◆ DDL_TMR_DMABURST_LENGTH_9TRANSFERS

#define DDL_TMR_DMABURST_LENGTH_9TRANSFERS (TMR_DCTRL_DBLEN_3)

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 909 of file g32r4xx_ddl_tmr.h.

Macros