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G32R430 Device Driver Layer v1.0.4
G32R4xx Device Driver Layer API Reference
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Macros | |
| #define | DDL_TMR_ETR_FILTER_FDIV1 (0x00000000U) |
| #define | DDL_TMR_ETR_FILTER_FDIV1_N2 (TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV1_N4 (TMR_SMCTRL_ETFCFG_1) |
| #define | DDL_TMR_ETR_FILTER_FDIV1_N8 (TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV2_N6 (TMR_SMCTRL_ETFCFG_2) |
| #define | DDL_TMR_ETR_FILTER_FDIV2_N8 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV4_N6 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1) |
| #define | DDL_TMR_ETR_FILTER_FDIV4_N8 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV8_N6 (TMR_SMCTRL_ETFCFG_3) |
| #define | DDL_TMR_ETR_FILTER_FDIV8_N8 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV16_N5 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1) |
| #define | DDL_TMR_ETR_FILTER_FDIV16_N6 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV16_N8 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2) |
| #define | DDL_TMR_ETR_FILTER_FDIV32_N5 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0) |
| #define | DDL_TMR_ETR_FILTER_FDIV32_N6 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1) |
| #define | DDL_TMR_ETR_FILTER_FDIV32_N8 (TMR_SMCTRL_ETFCFG) |
| #define DDL_TMR_ETR_FILTER_FDIV1 (0x00000000U) |
No filter, sampling is done at fDTS
Definition at line 826 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV16_N5 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1) |
fSAMPLING=fDTS/16, N=6
Definition at line 836 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV16_N6 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fDTS/16, N=8
Definition at line 837 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV16_N8 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2) |
fSAMPLING=fDTS/16, N=5
Definition at line 838 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV1_N2 (TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fCK_INT, N=2
Definition at line 827 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV1_N4 (TMR_SMCTRL_ETFCFG_1) |
fSAMPLING=fCK_INT, N=4
Definition at line 828 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV1_N8 (TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fCK_INT, N=8
Definition at line 829 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV2_N6 (TMR_SMCTRL_ETFCFG_2) |
fSAMPLING=fDTS/2, N=6
Definition at line 830 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV2_N8 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fDTS/2, N=8
Definition at line 831 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV32_N5 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fDTS/32, N=5
Definition at line 839 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV32_N6 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1) |
fSAMPLING=fDTS/32, N=6
Definition at line 840 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV32_N8 (TMR_SMCTRL_ETFCFG) |
fSAMPLING=fDTS/32, N=8
Definition at line 841 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV4_N6 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1) |
fSAMPLING=fDTS/4, N=6
Definition at line 832 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV4_N8 (TMR_SMCTRL_ETFCFG_2 | TMR_SMCTRL_ETFCFG_1 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fDTS/4, N=8
Definition at line 833 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV8_N6 (TMR_SMCTRL_ETFCFG_3) |
fSAMPLING=fDTS/8, N=8
Definition at line 834 of file g32r4xx_ddl_tmr.h.
| #define DDL_TMR_ETR_FILTER_FDIV8_N8 (TMR_SMCTRL_ETFCFG_3 | TMR_SMCTRL_ETFCFG_0) |
fSAMPLING=fDTS/16, N=5
Definition at line 835 of file g32r4xx_ddl_tmr.h.