Trigger Output

Macros
#define	DDL_TMR_TRGO_RESET   (0x00000000U)
#define	DDL_TMR_TRGO_ENABLE   (TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_UPDATE   (TMR_CTRL2_MMSEL_1)
#define	DDL_TMR_TRGO_CC1IF   (TMR_CTRL2_MMSEL_1 | TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_OC1REF   (TMR_CTRL2_MMSEL_2)
#define	DDL_TMR_TRGO_OC2REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_0)
#define	DDL_TMR_TRGO_OC3REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_1)
#define	DDL_TMR_TRGO_OC4REF   (TMR_CTRL2_MMSEL)

Detailed Description

Macro Definition Documentation

DDL_TMR_TRGO_CC1IF

#define DDL_TMR_TRGO_CC1IF   (TMR_CTRL2_MMSEL_1 | TMR_CTRL2_MMSEL_0)

CC1 capture or a compare match is used as trigger output

Definition at line 768 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_ENABLE

#define DDL_TMR_TRGO_ENABLE   (TMR_CTRL2_MMSEL_0)

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 766 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_OC1REF

#define DDL_TMR_TRGO_OC1REF   (TMR_CTRL2_MMSEL_2)

OC1REF signal is used as trigger output

Definition at line 769 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_OC2REF

#define DDL_TMR_TRGO_OC2REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_0)

OC2REF signal is used as trigger output

Definition at line 770 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_OC3REF

#define DDL_TMR_TRGO_OC3REF   (TMR_CTRL2_MMSEL_2 | TMR_CTRL2_MMSEL_1)

OC3REF signal is used as trigger output

Definition at line 771 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_OC4REF

#define DDL_TMR_TRGO_OC4REF   (TMR_CTRL2_MMSEL)

OC4REF signal is used as trigger output

Definition at line 772 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_RESET

#define DDL_TMR_TRGO_RESET   (0x00000000U)

UG bit from the TMRx_EGR register is used as trigger output

Definition at line 765 of file g32r4xx_ddl_tmr.h.

DDL_TMR_TRGO_UPDATE

#define DDL_TMR_TRGO_UPDATE   (TMR_CTRL2_MMSEL_1)

Update event is used as trigger output

Definition at line 767 of file g32r4xx_ddl_tmr.h.