TMR Private Macros

Macros
#define	TMR_GET_CHANNEL_INDEX( __CHANNEL__)
	Convert channel id into channel index.
#define	TMR_CALC_DTS(__TMRCLK__, __CKD__)
	Calculate the deadtime sampling period(in ps).
#define	IS_DDL_TMR_COUNTERMODE(__VALUE__)
#define	IS_DDL_TMR_CLOCKDIVISION(__VALUE__)
#define	IS_DDL_TMR_OCMODE(__VALUE__)
#define	IS_DDL_TMR_OCSTATE(__VALUE__)
#define	IS_DDL_TMR_OCPOLARITY(__VALUE__)
#define	IS_DDL_TMR_OCIDLESTATE(__VALUE__)
#define	IS_DDL_TMR_ACTIVEINPUT(__VALUE__)
#define	IS_DDL_TMR_ICPSC(__VALUE__)
#define	IS_DDL_TMR_IC_FILTER(__VALUE__)
#define	IS_DDL_TMR_IC_POLARITY(__VALUE__)
#define	IS_DDL_TMR_ENCODERMODE(__VALUE__)
#define	IS_DDL_TMR_IC_POLARITY_ENCODER(__VALUE__)
#define	IS_DDL_TMR_OSSR_STATE(__VALUE__)
#define	IS_DDL_TMR_OSSI_STATE(__VALUE__)
#define	IS_DDL_TMR_LOCK_LEVEL(__VALUE__)
#define	IS_DDL_TMR_BREAK_STATE(__VALUE__)
#define	IS_DDL_TMR_BREAK_POLARITY(__VALUE__)
#define	IS_DDL_TMR_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Detailed Description

Macro Definition Documentation

IS_DDL_TMR_ACTIVEINPUT

#define IS_DDL_TMR_ACTIVEINPUT

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_ACTIVEINPUT_DIRECTTI) \
|| ((__VALUE__) == DDL_TMR_ACTIVEINPUT_INDIRECTTI) \
|| ((__VALUE__) == DDL_TMR_ACTIVEINPUT_TRC))

Definition at line 100 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_AUTOMATIC_OUTPUT_STATE

#define IS_DDL_TMR_AUTOMATIC_OUTPUT_STATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_AUTOMATICOUTPUT_DISABLE) \
|| ((__VALUE__) == DDL_TMR_AUTOMATICOUTPUT_ENABLE))

Definition at line 154 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_BREAK_POLARITY

#define IS_DDL_TMR_BREAK_POLARITY

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_BREAK_POLARITY_LOW) \
|| ((__VALUE__) == DDL_TMR_BREAK_POLARITY_HIGH))

Definition at line 151 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_BREAK_STATE

#define IS_DDL_TMR_BREAK_STATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_BREAK_DISABLE) \
|| ((__VALUE__) == DDL_TMR_BREAK_ENABLE))

Definition at line 148 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_CLOCKDIVISION

#define IS_DDL_TMR_CLOCKDIVISION

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV1) \
|| ((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV2) \
|| ((__VALUE__) == DDL_TMR_CLOCKDIVISION_DIV4))

Definition at line 78 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_COUNTERMODE

#define IS_DDL_TMR_COUNTERMODE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_COUNTERMODE_UP) \
|| ((__VALUE__) == DDL_TMR_COUNTERMODE_DOWN) \
|| ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_UP) \
|| ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_DOWN) \
|| ((__VALUE__) == DDL_TMR_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 72 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_ENCODERMODE

#define IS_DDL_TMR_ENCODERMODE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_ENCODERMODE_X2_TI1) \
|| ((__VALUE__) == DDL_TMR_ENCODERMODE_X2_TI2) \
|| ((__VALUE__) == DDL_TMR_ENCODERMODE_X4_TI12))

Definition at line 130 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_IC_FILTER

#define IS_DDL_TMR_IC_FILTER

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N2) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N4) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV1_N8) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV2_N6) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV2_N8) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV4_N6) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV4_N8) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV8_N6) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV8_N8) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N5) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N6) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV16_N8) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N5) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N6) \
|| ((__VALUE__) == DDL_TMR_IC_FILTER_FDIV32_N8))

Definition at line 109 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_IC_POLARITY

#define IS_DDL_TMR_IC_POLARITY

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_IC_POLARITY_RISING) \
|| ((__VALUE__) == DDL_TMR_IC_POLARITY_FALLING) \
|| ((__VALUE__) == DDL_TMR_IC_POLARITY_BOTHEDGE))

Definition at line 126 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_IC_POLARITY_ENCODER

#define IS_DDL_TMR_IC_POLARITY_ENCODER

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_IC_POLARITY_RISING) \
|| ((__VALUE__) == DDL_TMR_IC_POLARITY_FALLING))

Definition at line 134 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_ICPSC

#define IS_DDL_TMR_ICPSC

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_ICPSC_DIV1) \
|| ((__VALUE__) == DDL_TMR_ICPSC_DIV2) \
|| ((__VALUE__) == DDL_TMR_ICPSC_DIV4) \
|| ((__VALUE__) == DDL_TMR_ICPSC_DIV8))

Definition at line 104 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_LOCK_LEVEL

#define IS_DDL_TMR_LOCK_LEVEL

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_LOCKLEVEL_OFF) \
|| ((__VALUE__) == DDL_TMR_LOCKLEVEL_1)   \
|| ((__VALUE__) == DDL_TMR_LOCKLEVEL_2)   \
|| ((__VALUE__) == DDL_TMR_LOCKLEVEL_3))

Definition at line 143 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OCIDLESTATE

#define IS_DDL_TMR_OCIDLESTATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OCIDLESTATE_LOW) \
|| ((__VALUE__) == DDL_TMR_OCIDLESTATE_HIGH))

Definition at line 97 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OCMODE

#define IS_DDL_TMR_OCMODE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OCMODE_FROZEN) \
|| ((__VALUE__) == DDL_TMR_OCMODE_ACTIVE) \
|| ((__VALUE__) == DDL_TMR_OCMODE_INACTIVE) \
|| ((__VALUE__) == DDL_TMR_OCMODE_TOGGLE) \
|| ((__VALUE__) == DDL_TMR_OCMODE_FORCED_INACTIVE) \
|| ((__VALUE__) == DDL_TMR_OCMODE_FORCED_ACTIVE) \
|| ((__VALUE__) == DDL_TMR_OCMODE_PWM1) \
|| ((__VALUE__) == DDL_TMR_OCMODE_PWM2))

Definition at line 82 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OCPOLARITY

#define IS_DDL_TMR_OCPOLARITY

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OCPOLARITY_HIGH) \
|| ((__VALUE__) == DDL_TMR_OCPOLARITY_LOW))

Definition at line 94 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OCSTATE

#define IS_DDL_TMR_OCSTATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OCSTATE_DISABLE) \
|| ((__VALUE__) == DDL_TMR_OCSTATE_ENABLE))

Definition at line 91 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OSSI_STATE

#define IS_DDL_TMR_OSSI_STATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OSSI_DISABLE) \
|| ((__VALUE__) == DDL_TMR_OSSI_ENABLE))

Definition at line 140 of file g32r4xx_ddl_tmr.c.

IS_DDL_TMR_OSSR_STATE

#define IS_DDL_TMR_OSSR_STATE

(

__VALUE__

)

Value:

(((__VALUE__) == DDL_TMR_OSSR_DISABLE) \
|| ((__VALUE__) == DDL_TMR_OSSR_ENABLE))

Definition at line 137 of file g32r4xx_ddl_tmr.c.

TMR_CALC_DTS

#define TMR_CALC_DTS	(		__TMRCLK__,
			__CKD__ )

Value:

(((__CKD__) == DDL_TMR_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TMRCLK__))         : \
 ((__CKD__) == DDL_TMR_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TMRCLK__) >> 1U)) : \
 ((uint64_t)1000000000000U/((__TMRCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters

__TMRCLK__	timer input clock frequency (in Hz).
__CKD__	This parameter can be one of the following values: DDL_TMR_CLOCKDIVISION_DIV1 DDL_TMR_CLOCKDIVISION_DIV2 DDL_TMR_CLOCKDIVISION_DIV4

Return values

none

Definition at line 177 of file g32r4xx_ddl_tmr.h.

TMR_GET_CHANNEL_INDEX

#define TMR_GET_CHANNEL_INDEX

(

__CHANNEL__

)

Value:

(((__CHANNEL__) == DDL_TMR_CHANNEL_CH1) ? 0U :\
 ((__CHANNEL__) == DDL_TMR_CHANNEL_CH1N) ? 1U :\
 ((__CHANNEL__) == DDL_TMR_CHANNEL_CH2) ? 2U :\
 ((__CHANNEL__) == DDL_TMR_CHANNEL_CH2N) ? 3U :\
 ((__CHANNEL__) == DDL_TMR_CHANNEL_CH3) ? 4U :\
 ((__CHANNEL__) == DDL_TMR_CHANNEL_CH3N) ? 5U : 6U)

Convert channel id into channel index.

Parameters

__CHANNEL__

This parameter can be one of the following values: DDL_TMR_CHANNEL_CH1 DDL_TMR_CHANNEL_CH1N DDL_TMR_CHANNEL_CH2 DDL_TMR_CHANNEL_CH2N DDL_TMR_CHANNEL_CH3 DDL_TMR_CHANNEL_CH3N DDL_TMR_CHANNEL_CH4

Return values

none

Definition at line 161 of file g32r4xx_ddl_tmr.h.