IT Defines

IT defines which can be used with DDL_USART_ReadReg and DDL_USART_WriteReg functions. More...

Macros
#define	DDL_USART_CTRL1_IDLEIEN   USART_CTRL1_IDLEIEN
#define	DDL_USART_CTRL1_RXBNEIEN   USART_CTRL1_RXBNEIEN
#define	DDL_USART_CTRL1_TXCIEN   USART_CTRL1_TXCIEN
#define	DDL_USART_CTRL1_TXBEIEN   USART_CTRL1_TXBEIEN
#define	DDL_USART_CTRL1_PEIEN   USART_CTRL1_PEIEN
#define	DDL_USART_CTRL2_LBDIEN   USART_CTRL2_LBDIEN
#define	DDL_USART_CTRL3_ERRIEN   USART_CTRL3_ERRIEN
#define	DDL_USART_CTRL3_CTSIEN   USART_CTRL3_CTSIEN

Detailed Description

IT defines which can be used with DDL_USART_ReadReg and DDL_USART_WriteReg functions.

Macro Definition Documentation

DDL_USART_CTRL1_IDLEIEN

#define DDL_USART_CTRL1_IDLEIEN   USART_CTRL1_IDLEIEN

IDLE interrupt enable

Definition at line 200 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL1_PEIEN

#define DDL_USART_CTRL1_PEIEN   USART_CTRL1_PEIEN

Parity error

Definition at line 204 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL1_RXBNEIEN

#define DDL_USART_CTRL1_RXBNEIEN   USART_CTRL1_RXBNEIEN

Read data register not empty interrupt enable

Definition at line 201 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL1_TXBEIEN

#define DDL_USART_CTRL1_TXBEIEN   USART_CTRL1_TXBEIEN

Transmit data register empty interrupt enable

Definition at line 203 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL1_TXCIEN

#define DDL_USART_CTRL1_TXCIEN   USART_CTRL1_TXCIEN

Transmission complete interrupt enable

Definition at line 202 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL2_LBDIEN

#define DDL_USART_CTRL2_LBDIEN   USART_CTRL2_LBDIEN

LIN break detection interrupt enable

Definition at line 205 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL3_CTSIEN

#define DDL_USART_CTRL3_CTSIEN   USART_CTRL3_CTSIEN

CTS interrupt enable

Definition at line 207 of file g32r4xx_ddl_usart.h.

DDL_USART_CTRL3_ERRIEN

#define DDL_USART_CTRL3_ERRIEN   USART_CTRL3_ERRIEN

Error interrupt enable

Definition at line 206 of file g32r4xx_ddl_usart.h.