One-stop MCU/SoC Technology Platform

The MCU/SoC can be customized according to the customer's requirements (including CPU instruction set customization) and controlled independently based on the CPU core.

Embedded eSE Security Unit Technology

As a single-chip embedded module, the security subsystem is crucial to ensure chip devices' security and relevant data information security.

eSE security link

  • Security defence
  • Physical isolation
  • Hardware secure startup
  • Life cycle management
  • Storage access management

eSE leadership

  • Adopt more comprehensive security protection mechanism to enhance security.
  • Both security and master control functions support customized application functions.
  • Systems only interact through the internal security communication interfaces, being safe and efficient.
  • Enables higher integration, lower power consumption, and higher security compared to the traditional multi-core solution.

Trusted CPU + Security CPU

The critical information such as keys/certificates are placed in a safe state and managed by the security OS.

As a black box, security OS only provides service, while the attacker cannot obtain its code or working principle.

Trusted CPU-based SoC

Trusted CPU

Trusted CPU

Adopt CK803S core

Introduce trusted implementation technology

Security CPU

Adopt CK802 core

19 customizable security mechanisms

Five Core Technologies of Security Encryption

Multi-scenario ultra-low-power technology

  • Run mode

    20mA: The basic protocol stack running on CPU 36MHz clock

    100mA: The protocol stack full speed running on CPU 144MHz clock

  • Standby mode

    2.5μA: The chip under to-wake-up status, supporting external trigger, timing, and other wake-up sources

  • Sleep mode

    1μA: the chip under long sleep status, reducing energy consumption, while regular wakeup is supported

Autonomous processor customization technology

  • Universal embedded CPU design

    Domestic, independent C-SKY V2 32 / 16-bit mixed RISC CPU

    RISC-V instruction set architecture RISC CPU

    Custom instruction set RISC/CISC CPU

  • Dedicated processing unit design

    Universal processor DSP instruction extension

    DSP, ASIP, hardware accelerator

High-reliability anti-jamming technology

  • High-reliability design technology

    Customized ESD technology and optimization: > 8KV HBM ESD

    Customized EMC technology and optimization

  • Spread spectrum clock technology

    Spread spectrum OSC and PLL technology

  • Dynamic monitoring and adjusting technology for temperature and voltage

    Real time monitoring for chip’s junction temperature and voltage drop

    Adjust the chip run mode to ensure stable running.

Fault-tolerant computing architecture technology

  • Dual-core Lock-step synchronous interlocking structure

    Fault detection, recovery, isolation

  • Strong verification technology for storage and communication

SDK

  • Support RTOS and SeCoS system

  • Handy driver interface

  • Complete TCP/IP protocol stack

  • GP-standard API

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