Printer Controller SoC

GS500

Product Overview

Dachuan GS500 is a highly integrated security SoC, based on the domestic multi-core heterogeneous architecture, using high-performance system of CK810F CPU to handle system workload and run Linux operating system.Integrated rich system IP and peripheral IP, including USB 2.0 dual role controller, DDR2/3 controller, NAND flash controller, GMAC, SDIO 2.0, etc.Two CK803S CPUs were used to realize real-time response.Rich security IP (AES, DES, SHA, SM2/4);Support anti - fuse - out OTP, can realize key storage and restricted access to CPU.

Structure Diagram

Performance

System Architecture

  • Based on the CK810F, CK803S and CK802 cores
  • CK810F Maximum frequency 600MHz
  • CK803S, CK802 Maximum frequency 200MHz

Memory

  • SRAM：584KB
  • OTP：1KB
  • ROM：104KB

Timer

  • System clock: 1 x 24M crystal via clock generator clock generator for each SOC module Multiple clocks

Reset,Power management

  • Power-on Reset (POR)
  • General purpose GPIO power supply: 2.97~3.63V
  • Kernel system power supply: 0.99V~1.21V
  • DDR power supply: 1.425V~1.575V

Interrupt

  • Supports 64 interrupt resources

DMA

  • 3 DMA modules with 2 channels each

MailBox

  • 4 MailBoxes on CK810F, 2xCK803S and CK802 2xCK803S and CK802
  • Multi-core communication support

Security

  • Support for 128-bit/193-bit/256-bit AES
  • Support for 64-bit/192-bit 3DES
  • SM2, SM4
  • SHA Family
  • ECC

I/Os

  • 4 groups of GPIOs 32 ports each, all IOs can be mapped to interrupts

Timer

  • 2 x 32-bit system timers
  • 1 x 64-bit high resolution timer
  • 1 x 32-bit watchdog
  • 1 x 32-bit RTC

Peripherals

  • 1 NFC with NANDwFlash support
  • 1 SDC with SD card support
  • 1 LCDC, supports max. resolution 1280x800@60Hz
  • 9 UARTs
  • 5 SPI, support for data transfer directly to external SPI-Flash via DMA interface
  • 4 I2C, max. transfer speed 3.4Mb/s
  • 3 USBw2.0, master-slave mode support
  • 1 GMAC with DMA function

PWM

  • 3 x XPWMA and 1 x normal PWM

ADC

  • 1 low power, high speed, successive approximation type ADC that supports an advanced 1.0MSPS maximum sampling frequency and 12-bit sampling resolution, supporting 10 channels

DDR2/3

  • Supports up to 2G bytes per stage, x8 and x16 DDR2/DDR3 SDRAM

Image Processing

  • Supports JPEG, JBIG image encoding formats

Package

  • BGA525

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